公开(公告)号：US20200105735A1

公开(公告)日：2020-04-02

申请号：US16414083

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Mog PARK ,  Sang Youn JO

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/00

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

公开(公告)号：US20240062808A1

公开(公告)日：2024-02-22

申请号：US18460683

申请日：2023-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Sang Youn JO ,  Jee Hoon HAN

IPC: G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.

公开(公告)号：US20230268333A1

公开(公告)日：2023-08-24

申请号：US18140917

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Mog PARK ,  Sang Youn JO

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H10B41/27 ,  H10B41/30 ,  H10B41/40 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L23/528 ,  H01L24/09 ,  H01L24/05 ,  H01L25/50 ,  H01L24/89 ,  H01L24/08 ,  H10B41/27 ,  H10B41/30 ,  H10B41/40 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40 ,  H01L2224/80001 ,  H01L2224/0557 ,  H01L2224/08147 ,  H01L2224/0913

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

公开(公告)号：US20220189940A1

公开(公告)日：2022-06-16

申请号：US17687790

申请日：2022-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Mog PARK ,  Sang Youn JO

IPC: H01L25/18 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/00 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/00

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.

公开(公告)号：US20220101911A1

公开(公告)日：2022-03-31

申请号：US17465539

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS co., LTD.

Inventor： KOHJI KANAMORI ,  Sang Youn JO ,  Jee Hoon HAN

IPC: G11C11/4093 ,  H01L27/108

Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.

公开(公告)号：US20200381413A1

公开(公告)日：2020-12-03

申请号：US16994207

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Mog PARK ,  Sang Youn JO

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.