公开(公告)号：US10553647B2

公开(公告)日：2020-02-04

申请号：US16021804

申请日：2018-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael K. Grobis ,  Derek Stewart ,  Bruce D. Terris

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C13/00 ,  G11C11/16

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.

公开(公告)号：US10355049B1

公开(公告)日：2019-07-16

申请号：US16021776

申请日：2018-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael K. Grobis ,  Derek Stewart ,  Bruce D. Terris

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00 ,  G11C11/16 ,  G11C13/00

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element.

公开(公告)号：US20200006432A1

公开(公告)日：2020-01-02

申请号：US16021804

申请日：2018-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael K. Grobis ,  Derek Stewart ,  Bruce D. Terris

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C13/00 ,  G11C11/16

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.