公开(公告)号：US11778818B2

公开(公告)日：2023-10-03

申请号：US16934445

申请日：2020-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo Mochizuki ,  Yasuo Kasagi ,  Michiaki Sano ,  Junji Oh ,  Yujin Terasawa ,  Hiroaki Namba

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H01L23/522

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/35

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.

公开(公告)号：US20240015960A1

公开(公告)日：2024-01-11

申请号：US17857375

申请日：2022-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroaki Namba

IPC: H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack. In one embodiment, a connection via structure can vertically extend through the dielectric material portion, and a metal plate can contact the connection via structure. Alternately or additionally, an integrated via and pad structure may be provided, which includes a conductive via portion vertically extending through the dielectric material portion and a conductive pad portion located on an end of the conductive via portion.