公开(公告)号：US10957705B2

公开(公告)日：2021-03-23

申请号：US16231752

申请日：2018-12-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Totoki ,  Shigehisa Inoue ,  Yuki Kasai ,  Hironori Matsuoka

IPC: H01L27/11582 ,  G11C5/06 ,  H01L25/065 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.

公开(公告)号：US11515317B2

公开(公告)日：2022-11-29

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Junpei Kanazawa ,  Hisakazu Otoi ,  Hironori Matsuoka ,  Raiden Matsuno

IPC: H01L27/11582 ,  H01L27/11539 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.