公开(公告)号：US11515317B2

公开(公告)日：2022-11-29

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Junpei Kanazawa ,  Hisakazu Otoi ,  Hironori Matsuoka ,  Raiden Matsuno

IPC: H01L27/11582 ,  H01L27/11539 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

公开(公告)号：US10256252B1

公开(公告)日：2019-04-09

申请号：US15840090

申请日：2017-12-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Junpei Kanazawa

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11524 ,  H01L27/11526 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A bottommost insulating layer among the insulating layers comprises a first silicon oxide material, and at least some of the insulating layers other than the bottommost insulating layer include a second silicon oxide material having a greater density than the first silicon oxide material.

公开(公告)号：US10937801B2

公开(公告)日：2021-03-02

申请号：US16361773

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Koichiro Nagata ,  Junpei Kanazawa

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.

公开(公告)号：US11282783B2

公开(公告)日：2022-03-22

申请号：US16809861

申请日：2020-03-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Masanori Terahara ,  Junpei Kanazawa

IPC: H01L23/52 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L29/66 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.