公开(公告)号：US20240096826A1

公开(公告)日：2024-03-21

申请号：US17947672

申请日：2022-09-19

Applicant: SanDisk Technologies LLC

Inventor： Guangyuan Li ,  Yuji Totoki ,  Fumiaki Toyama

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02311 ,  H01L2224/02331

Abstract: An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.

公开(公告)号：US11488975B2

公开(公告)日：2022-11-01

申请号：US17081458

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Totoki ,  Fumitaka Amano

IPC: H01L27/115 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/3205 ,  H01L27/11573 ,  H01L27/11531

Abstract: A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.

公开(公告)号：US11844222B2

公开(公告)日：2023-12-12

申请号：US17146866

申请日：2021-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke Takuma ,  Yuji Totoki ,  Seiji Shimabukuro ,  Tatsuya Hinoue ,  Kengo Kajiwara ,  Akihiro Tobioka

IPC: H10B43/50 ,  H01L23/522 ,  H01L23/00 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US10957705B2

公开(公告)日：2021-03-23

申请号：US16231752

申请日：2018-12-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuji Totoki ,  Shigehisa Inoue ,  Yuki Kasai ,  Hironori Matsuoka

IPC: H01L27/11582 ,  G11C5/06 ,  H01L25/065 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies.

公开(公告)号：US11637038B2

公开(公告)日：2023-04-25

申请号：US17153972

申请日：2021-01-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Yuji Totoki ,  Shunsuke Takuma

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack that underlies the retro-stepped dielectric material portion. Some of the pillar-shaped contact-opening assemblies can include a first conductive plug that laterally contacts a cylindrical sidewall of a respective one of the electrically conductive layers and a conductive via structure that contacts a top surface of the first conductive plug.