公开(公告)号：US12279425B2

公开(公告)日：2025-04-15

申请号：US17411726

申请日：2021-08-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

公开(公告)号：US12029036B2

公开(公告)日：2024-07-02

申请号：US17244258

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

公开(公告)号：US11997850B2

公开(公告)日：2024-05-28

申请号：US17411689

申请日：2021-08-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura

IPC: H10B41/35 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

公开(公告)号：US12250814B2

公开(公告)日：2025-03-11

申请号：US17806579

申请日：2022-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura ,  Takayuki Maekura

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.