公开(公告)号：US12127406B2

公开(公告)日：2024-10-22

申请号：US17577533

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Takashi Inomata ,  Takayuki Maekura

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/535 ,  H01L25/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B51/30 ,  H10B63/00

CPC classification number: H10B43/27 ,  H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B51/20 ,  H10B51/30 ,  H10B63/34 ,  H10B63/845 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1441 ,  H01L2924/1444 ,  H01L2924/14511

Abstract: A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

公开(公告)号：US11355506B2

公开(公告)日：2022-06-07

申请号：US16881346

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi Tokita ,  Takayuki Maekura ,  Romain Mentek

IPC: H01L27/11556 ,  H01L23/528 ,  H01L25/065 ,  H01L23/522 ,  H01L21/822 ,  H01L27/11519 ,  H01L27/11524

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers.

公开(公告)号：US12250814B2

公开(公告)日：2025-03-11

申请号：US17806579

申请日：2022-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi Shimomura ,  Takayuki Maekura

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.

公开(公告)号：US11367736B2

公开(公告)日：2022-06-21

申请号：US16881401

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi Tokita ,  Takayuki Maekura ,  Romain Mentek

IPC: H01L25/065 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11524

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers.