公开(公告)号：US12096632B2

公开(公告)日：2024-09-17

申请号：US17244311

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Johann Alsmeier

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

公开(公告)号：US11871580B2

公开(公告)日：2024-01-09

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng Zhang ,  Yanli Zhang ,  Xiang Yang ,  Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H10B51/30 ,  H01L21/764 ,  H01L29/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L21/764 ,  H01L29/0649 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20230163116A1

公开(公告)日：2023-05-25

申请号：US18100152

申请日：2023-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H10B43/40 ,  H01L2225/06541 ,  H10B41/27

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US11387142B1

公开(公告)日：2022-07-12

申请号：US17208019

申请日：2021-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529

Abstract: A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.

公开(公告)号：US11380707B2

公开(公告)日：2022-07-05

申请号：US17116093

申请日：2020-12-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Jixin Yu ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.

公开(公告)号：US12288755B2

公开(公告)日：2025-04-29

申请号：US17807266

申请日：2022-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno

IPC: H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.

公开(公告)号：US12255242B2

公开(公告)日：2025-03-18

申请号：US17587470

申请日：2022-01-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Koichi Matsuno

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H10B43/27

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

公开(公告)号：US20240179916A1

公开(公告)日：2024-05-30

申请号：US18221711

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Kota Funayama

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

公开(公告)号：US11856765B2

公开(公告)日：2023-12-26

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US10727216B1

公开(公告)日：2020-07-28

申请号：US16409593

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L21/76 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.