公开(公告)号：US10854513B2

公开(公告)日：2020-12-01

申请号：US16249352

申请日：2019-01-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoki Kawasaki ,  Toshiyuki Sega

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/535

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a semiconductor material layer. Memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer is formed on sidewalls of the backside trench. A first doped semiconductor material is deposited within the backside trench. Vertical cavities are formed by vertically recessing the first doped semiconductor material at discrete locations that are laterally spaced apart. A second doped semiconductor material is deposited in the vertical cavities. The second doped semiconductor material disrupts a laterally-extending cavity in the first doped semiconductor material, thereby providing a structurally reinforced network of the first and second doped semiconductor materials for a backside contact via structure that is formed in the backside trench.

公开(公告)号：US11935784B2

公开(公告)日：2024-03-19

申请号：US17345315

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Yusuke Osawa ,  Kensuke Ishikawa ,  Mitsuteru Mushiga ,  Motoki Kawasaki ,  Shinsuke Yada ,  Masato Miyamoto ,  Syo Fukata ,  Takashi Kashimura ,  Shigehiro Fujino

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H01L23/535 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

公开(公告)号：US10804197B1

公开(公告)日：2020-10-13

申请号：US16516726

申请日：2019-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoki Kawasaki ,  Arata Okuyama ,  Xun Gu ,  Kengo Kajiwara ,  Jixin Yu

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.