公开(公告)号：US09711532B2

公开(公告)日：2017-07-18

申请号：US15292898

申请日：2016-10-13

Applicant: SanDisk Technologies LLC

Inventor： Masato Miyamoto ,  Yuji Fukano

IPC: H01L29/76 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/49 ,  H01L21/285 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/495

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.

公开(公告)号：US11935784B2

公开(公告)日：2024-03-19

申请号：US17345315

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Yusuke Osawa ,  Kensuke Ishikawa ,  Mitsuteru Mushiga ,  Motoki Kawasaki ,  Shinsuke Yada ,  Masato Miyamoto ,  Syo Fukata ,  Takashi Kashimura ,  Shigehiro Fujino

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H01L23/535 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

公开(公告)号：US20170033121A1

公开(公告)日：2017-02-02

申请号：US15292898

申请日：2016-10-13

Applicant: SanDisk Technologies LLC

Inventor： Masato Miyamoto ,  Yuji Fukano

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/495

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.

Abstract translation: 提供了一种用于3D叠层非易失性存储器件的制造工艺，其提供源接触到堆叠中的存储器孔的底部，而不暴露存储器孔的内侧壁的可编程材料衬里，并且不暴露沟道形成区域 还将记忆孔的内部衬在能量和潜在的破坏性蚀刻环境中。 堆叠包括交替的控制栅极层和介电层在衬底上，并且通过堆叠蚀刻存储器孔，然后利用可编程材料，然后与沟道形成材料衬里其内侧壁。 该过程避免了通过存储器孔进行大量蚀刻的需要，以通过替代地从存储器孔下方向上蚀刻而在通道形成材料的底部附近打开源接触孔。