公开(公告)号：US11637119B2

公开(公告)日：2023-04-25

申请号：US17134938

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kohei Yamaguchi ,  Keisuke Shigemura ,  Kengo Kajiwara

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11529

Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.

公开(公告)号：US11637118B2

公开(公告)日：2023-04-25

申请号：US17036070

申请日：2020-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke Takuma ,  Seiji Shimabukuro ,  Kengo Kajiwara

IPC: H01L27/11575 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11556

Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.

公开(公告)号：US11844222B2

公开(公告)日：2023-12-12

申请号：US17146866

申请日：2021-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke Takuma ,  Yuji Totoki ,  Seiji Shimabukuro ,  Tatsuya Hinoue ,  Kengo Kajiwara ,  Akihiro Tobioka

IPC: H10B43/50 ,  H01L23/522 ,  H01L23/00 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20180151588A1

公开(公告)日：2018-05-31

申请号：US15361842

申请日：2016-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kengo Kajiwara ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.

公开(公告)号：US10804197B1

公开(公告)日：2020-10-13

申请号：US16516726

申请日：2019-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoki Kawasaki ,  Arata Okuyama ,  Xun Gu ,  Kengo Kajiwara ,  Jixin Yu

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.

公开(公告)号：US09991277B1

公开(公告)日：2018-06-05

申请号：US15361842

申请日：2016-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kengo Kajiwara ,  Raghuveer S. Makala

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.

公开(公告)号：US11018152B2

公开(公告)日：2021-05-25

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya Hinoue ,  Kengo Kajiwara ,  Ryousuke Itou ,  Naohiro Hosoda

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

公开(公告)号：US09754999B1

公开(公告)日：2017-09-05

申请号：US15240998

申请日：2016-08-18

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada ,  Yusuke Oda

IPC: H01L27/11551 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/2454 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/249 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

公开(公告)号：US09673257B1

公开(公告)日：2017-06-06

申请号：US15172483

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Akira Nakada ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/66 ,  H01L29/51 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/786 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.