公开(公告)号：US20210057336A1

公开(公告)日：2021-02-25

申请号：US16547971

申请日：2019-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian SHAO ,  Jee-Yeon KIM ,  Fumiaki TOYAMA ,  Hirofumi TOKITA

IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.

公开(公告)号：US20220367393A1

公开(公告)日：2022-11-17

申请号：US17317442

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian SHAO ,  Fumiaki TOYAMA ,  Peter RABKIN

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L49/02 ,  H01L25/00

Abstract: A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

公开(公告)号：US20240006310A1

公开(公告)日：2024-01-04

申请号：US17810124

申请日：2022-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO ,  Hirofumi TOKITA ,  Shiqian SHAO ,  Fumiaki TOYAMA

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity. Alternatively or additionally, a top portion of the stepped cavity and a width of a bridge region of the electrically conductive layers in the inter-array region may have a variable lateral extent along the second horizontal direction.

公开(公告)号：US20240005990A1

公开(公告)日：2024-01-04

申请号：US17810097

申请日：2022-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi TOKITA ,  Tomohiro KUBO ,  Shiqian SHAO ,  Fumiaki TOYAMA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity. Alternatively or additionally, a top portion of the stepped cavity and a width of a bridge region of the electrically conductive layers in the inter-array region may have a variable lateral extent along the second horizontal direction.