公开(公告)号：US20220375958A1

公开(公告)日：2022-11-24

申请号：US17328302

申请日：2021-05-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji SHIMABUKURO ,  Takashi YAMAHA

IPC: H01L27/11575 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/11595 ,  H01L27/11597 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through a first region of the alternating stack, memory opening fill structures located in the memory openings, and support pillar structures vertically extending through a second region of the alternating stack. Each of the support pillar structures includes a central columnar structure and a set of fins laterally protruding from the central columnar structure at levels of a subset of the electrically conductive layers.

公开(公告)号：US20240213094A1

公开(公告)日：2024-06-27

申请号：US18355029

申请日：2023-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi YAMAHA

IPC: H01L21/768 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H10B43/27

Abstract: An integrated line-and-via structure includes a metal line structure including a first metal and having a pair of lengthwise metal line sidewalls that laterally extend along a first horizontal direction, a metallic capping plate including a metallic capping material and overlying the metal line structure and having a pair of lengthwise metal cap sidewalls that are vertically coincident with the pair of lengthwise metal line sidewalls, and a metal via structure including a second metal and having a pair of lengthwise metal via sidewalls that is vertically coincident with the pair of lengthwise metal cap sidewalls and having a lateral extent along the first horizontal direction that is less than a lateral extent of the metal line structure along the first horizontal direction.

公开(公告)号：US20230130849A1

公开(公告)日：2023-04-27

申请号：US18059698

申请日：2022-11-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi YAMAHA ,  Tatsuya HINOUE ,  Fumitaka AMANO

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A metal interconnect assembly includes a first metal interconnect structure, and a second metal interconnect structure embedded in a second dielectric material layer and containing a metal line portion having a top surface located within a first horizontal plane and having a bottom surface located within a second horizontal plane, and further containing a metal via portion adjoined to a bottom of the metal line portion and contacting a top surface of the first metal interconnect structure. The second metal interconnect structure contains a metallic liner including a first metallic material that includes an entire volume of the metal via portion and an outer part of the metal line portion, and a metallic fill material portion contains a second metallic material that includes an inner part of the metal line portion, does not contact and is spaced from the second dielectric material layer by the metallic liner.

公开(公告)号：US20200321324A1

公开(公告)日：2020-10-08

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi YAMAHA ,  Koichi ITO ,  Ikue YOKOMIZO ,  Ryo HIRAMATSU ,  Kazuto WATANABE ,  Katsuya KATO ,  Hajime YAMAMOTO ,  Hiroshi SASAKI

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.