公开(公告)号：US20220005824A1

公开(公告)日：2022-01-06

申请号：US16918463

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu TANAKA ,  Koichi ITO ,  Hideaki HASEGAWA ,  Akihiro TOBIOKA ,  Sung Tae LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US20210242128A1

公开(公告)日：2021-08-05

申请号：US16782307

申请日：2020-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi ITO ,  Yoshinobu TANAKA ,  Hirofumi TOKITA

IPC: H01L23/528 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.

公开(公告)号：US20220189872A1

公开(公告)日：2022-06-16

申请号：US17684922

申请日：2022-03-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki SANO ,  Koichi ITO

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/528

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and an insulating spacer laterally surrounding the contact via structure and having an outer surface having a corrugated vertical cross-sectional profile in which first portions of the insulating spacer located at levels of the electrically conductive layers laterally protrude outward relative to second portions of the insulating spacer located at levels of the insulating layers.

公开(公告)号：US20220005818A1

公开(公告)日：2022-01-06

申请号：US16918493

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu TANAKA ,  Koichi ITO ,  Hideaki HASEGAWA ,  Akihiro TOBIOKA ,  Sung Tae LEE

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US20230380151A1

公开(公告)日：2023-11-23

申请号：US17663951

申请日：2022-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki SANO ,  Koichi ITO ,  Takyua MORI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word lines and drain select gate electrodes that contain plurality of drain-select-level electrically conductive strips which are located above the word lines, memory stack structures vertically extending through the alternating stack, drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips, and a first laterally-insulated contact via assembly including a first layer contact via structure and a first tubular insulating spacer. The first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines, and the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures.

公开(公告)号：US20200321324A1

公开(公告)日：2020-10-08

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi YAMAHA ,  Koichi ITO ,  Ikue YOKOMIZO ,  Ryo HIRAMATSU ,  Kazuto WATANABE ,  Katsuya KATO ,  Hajime YAMAMOTO ,  Hiroshi SASAKI

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.