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1.发明申请公开(公告)号：US20220406793A1
公开(公告)日：2022-12-22
申请号：US17351756
申请日：2021-06-18
IPC分类号： H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11565
摘要： A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
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2.发明申请公开(公告)号：US20210388502A1
公开(公告)日：2021-12-16
申请号：US16897717
申请日：2020-06-10
发明人： Seiji SHIMABUKURO , Makoto TSUTSUE
IPC分类号： C23C16/56 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , C23C16/04 , C23C16/34 , H01J37/32
摘要： A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.
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3.发明申请公开(公告)号：US20210388500A1
公开(公告)日：2021-12-16
申请号：US16897679
申请日：2020-06-10
发明人： Seiji SHIMABUKURO , Makoto TSUTSUE
IPC分类号： C23C16/509 , H01J37/32 , H01L21/02 , H01L27/11556 , H01L21/67 , H01L27/11582 , H01L21/677 , C23C16/34
摘要： A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.
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4.发明申请公开(公告)号：US20180374865A1
公开(公告)日：2018-12-27
申请号：US15632983
申请日：2017-06-26
IPC分类号： H01L27/11582 , H01L27/11556 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/66 , H01L23/535
CPC分类号： H01L27/11582 , H01L23/535 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/66553 , H01L29/66825 , H01L29/66833 , H01L29/7849 , H01L29/7889 , H01L29/7926
摘要： An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. A retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material on stepped surfaces of the alternating stack. Memory stack structures are formed through the first-tier alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a memory film. A patterned tensile-stress-generating material layer is formed over the retro-stepped dielectric material portion in a region that is laterally spaced outward from an outer periphery of a topmost layer within the alternating stack. The patterned tensile-stress-generating material layer applies a tensile stress to the retro-stepped dielectric material portion and to the alternating stack to compensate for the compressive stress generated by the retro-stepped dielectric material portion.
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5.发明申请公开(公告)号：US20220406379A1
公开(公告)日：2022-12-22
申请号：US17351789
申请日：2021-06-18
IPC分类号： G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L27/1157 , H01L23/522 , H01L23/528
摘要： A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
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公开(公告)号：US20220254733A1
公开(公告)日：2022-08-11
申请号：US17174064
申请日：2021-02-11
发明人： Genta MIZUNO , Kenzo IIZUKA , Satoshi SHIMIZU , Keisuke IZUMI , Tatsuya HINOUE , Yujin TERASAWA , Seiji SHIMABUKURO , Ryousuke ITOU , Yanli ZHANG , Johann ALSMEIER , Yusuke YOSHIDA
IPC分类号： H01L23/00 , H01L23/522 , H01L27/11556 , H01L27/11582
摘要： A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.
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7.发明申请公开(公告)号：US20190221574A1
公开(公告)日：2019-07-18
申请号：US15956139
申请日：2018-04-18
IPC分类号： H01L27/11578 , H01L29/792 , H01L27/11551 , H01L27/105 , H01L27/1157 , H01L27/11543 , G11C16/04
摘要： A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.
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8.发明公开公开(公告)号：US20240260266A1
公开(公告)日：2024-08-01
申请号：US18356896
申请日：2023-07-21
发明人： Naohiro HOSODA , Masanori TSUTSUMI , Shunsuke TAKUMA , Seiji SHIMABUKURO , Tatsuya HINOUE , Takashi KASHIMURA , Tomohiro KUBO , Hisakazu OTOI , Hiroyuki TANAKA , Takumi MORIYAMA , Ryota SUZUKI
摘要： A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.
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9.发明公开公开(公告)号：US20240099014A1
公开(公告)日：2024-03-21
申请号：US18524552
申请日：2023-11-30
发明人： Shunsuke TAKUMA , Yuji TOTOKI , Seiji SHIMABUKURO , Tatsuya HINOUE , Kengo KAJIWARA , Akihiro TOBIOKA
CPC分类号： H10B43/50 , H01L23/5226 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.
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10.发明申请公开(公告)号：US20220406720A1
公开(公告)日：2022-12-22
申请号：US17351811
申请日：2021-06-18
IPC分类号： H01L23/535 , H01L23/522 , H01L23/532 , H01L27/11556 , H01L27/11582 , H01L21/768
摘要： A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
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