公开(公告)号：US20220415907A1

公开(公告)日：2022-12-29

申请号：US17355883

申请日：2021-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto WATANABE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.

公开(公告)号：US20240096694A1

公开(公告)日：2024-03-21

申请号：US17932887

申请日：2022-09-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto WATANABE

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76843

Abstract: A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

公开(公告)号：US20230276625A1

公开(公告)日：2023-08-31

申请号：US17682550

申请日：2022-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto WATANABE ,  Youko FURIHATA

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/5226

Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.

公开(公告)号：US20200321324A1

公开(公告)日：2020-10-08

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi YAMAHA ,  Koichi ITO ,  Ikue YOKOMIZO ,  Ryo HIRAMATSU ,  Kazuto WATANABE ,  Katsuya KATO ,  Hajime YAMAMOTO ,  Hiroshi SASAKI

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.