公开(公告)号：US20220005818A1

公开(公告)日：2022-01-06

申请号：US16918493

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu TANAKA ,  Koichi ITO ,  Hideaki HASEGAWA ,  Akihiro TOBIOKA ,  Sung Tae LEE

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US20190280001A1

公开(公告)日：2019-09-12

申请号：US16002265

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yujin TERASAWA ,  Genta MIZUNO ,  Yusuke MUKAE ,  Yoshinobu TANAKA ,  Shiori KATAOKA ,  Ryosuke ITOU ,  Kensuke YAMAGUCHI ,  Naoki TAKEGUCHI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.

公开(公告)号：US20220005824A1

公开(公告)日：2022-01-06

申请号：US16918463

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu TANAKA ,  Koichi ITO ,  Hideaki HASEGAWA ,  Akihiro TOBIOKA ,  Sung Tae LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US20210242128A1

公开(公告)日：2021-08-05

申请号：US16782307

申请日：2020-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi ITO ,  Yoshinobu TANAKA ,  Hirofumi TOKITA

IPC: H01L23/528 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.