公开(公告)号：US20240426883A1

公开(公告)日：2024-12-26

申请号：US18687909

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Niuyi SUN ,  Dan YANG ,  Na MEI ,  Tuobei SUN

IPC: G01R27/08 ,  G01R1/20 ,  G01R31/26

Abstract: A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the encapsulation network resistor Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.

公开(公告)号：US20240036123A1

公开(公告)日：2024-02-01

申请号：US18265358

申请日：2021-11-25

Applicant: SANECHIPS TECHNOLOGY CO., LTD

Inventor： Niuyi SUN ,  Dan YANG ,  Na MEI ,  Tuobei SUN

IPC: G01R31/71 ,  G01R27/14

CPC classification number: G01R31/71 ,  G01R27/14

Abstract: Disclosed are a method and an apparatus for measuring electromigration of solder joints. The method includes: determining, according to voltage test pads led out from both ends of one or more solder joints, a voltage of a daisy subchain between the one or more solder joints (S502); and determining, according to the voltage, a resistance of the one or more solder joints (S504).

公开(公告)号：US20250106980A1

公开(公告)日：2025-03-27

申请号：US18725768

申请日：2022-02-25

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Qiang JIANG ,  Leqi LI ,  Zongwei WANG ,  Jian PANG ,  Tuobei SUN

IPC: H05K1/02 ,  H05K1/11

Abstract: The embodiments of the present application relate to the technical field of integrated circuit packaging. Provided are a packaging structure and an integrated circuit board. The packaging structure includes: a substrate having a plurality of first conductive layers and a plurality of second conductive layers, where the first conductive layers and the second conductive layers have different electric property types; a redistribution structure including redistribution layers at a plurality of layers and arranged at intervals, wherein the redistribution layers located at the same layer have the same electric property type, and the redistribution layers located at adjacent layers have different electric property types; and a plurality of conductive bumps electrically connected to the first conductive layers or the second conductive layers through the redistribution structure.

公开(公告)号：US20240264104A1

公开(公告)日：2024-08-08

申请号：US18565582

申请日：2022-03-14

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Niuyi SUN ,  Dan YANG ,  Na MEI ,  Tuobei SUN

IPC: G01N27/04

CPC classification number: G01N27/045 ,  G01N27/041

Abstract: Disclosed is a test apparatus, including: a connection circuit having a plurality of mounting positions each configured to connect a sample; a detection unit configured to perform a detection on the sample; and a control unit configured to control the detection unit to perform the detection on the sample. Further disclosed is a test method, including: connecting a sample to a mounting position of a test apparatus; and perform a test on the sample with the test apparatus.