公开(公告)号：US08937365B2

公开(公告)日：2015-01-20

申请号：US14041022

申请日：2013-09-30

Applicant: Seiko Instruments Inc.

Inventor： Yukimasa Minami

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.

Abstract translation: 在包括用于进行激光修整处理的熔丝元件的半导体集成电路器件中，在由第二多晶Si膜形成的熔丝元件之间形成由第一多晶Si膜形成的虚拟熔丝，并且在虚拟熔丝上形成氮化物膜。 以这种方式，消除了由多晶Si膜形成的熔丝的存在和不存在引起的层间膜的阶差，从而防止在保险丝开口区域的内表面上具有吸湿特性的SOG膜， 在内部元件侧彼此连接。

公开(公告)号：US09231101B2

公开(公告)日：2016-01-05

申请号：US14478044

申请日：2014-09-05

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yukimasa Minami

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device includes a semiconductor substrate, a body region, a body contact region and a cancelling region each of the first conductivity type, and a buried layer, an epitaxial layer and a source region each of the second conductivity type. A trench is provided in the epitaxial layer from a surface thereof. A gate insulating film is provided on an inner wall of the trench, and a gate electrode made of polycrystalline silicon is in contact with the gate insulating film and fills the trench. The cancelling region, which is provided below a bottom surface of the trench for cancelling a conductivity type of the buried layer, has a distribution center located below a boundary surface between the buried layer and the epitaxial layer. A trench bottom surface lower region of the first conductivity type is provided from the bottom surface of the trench continuously to the cancelling region.

Abstract translation: 半导体器件包括第一导电类型的半导体衬底，主体区域，本体接触区域和抵消区域，以及第二导电类型的掩埋层，外延层和源极区域。 从其表面在外延层中提供沟槽。 栅极绝缘膜设置在沟槽的内壁上，并且由多晶硅制成的栅电极与栅极绝缘膜接触并填充沟槽。 设置在用于消除埋层的导电类型的沟槽的底表面下方的抵消区域具有位于掩埋层和外延层之间的边界面下方的分布中心。 第一导电类型的沟槽底表面下部区域从沟槽的底表面连续地提供到消除区域。

公开(公告)号：US08574974B2

公开(公告)日：2013-11-05

申请号：US13721228

申请日：2012-12-20

Applicant: Seiko Instruments Inc.

Inventor： Yukimasa Minami

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/148

CPC classification number: H01L21/82 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823885 ,  H01L29/0653 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.

Abstract translation: 在用于掩模的沟槽栅极上的区域以外的区域上形成光致抗蚀剂，蚀刻并除去沟槽栅电极上的第三栅极绝缘膜。 之后，在第二和第三栅极绝缘膜上以及在沟槽栅电极上形成非掺杂多晶硅层，并且通过使用分离的离子注入引入N型和P型高浓度杂质 具有低击穿电压和高击穿电压的NMOS晶体管和PMOS晶体管的多晶硅层上的掩模。 然后，通过各向异性蚀刻形成第二栅电极。 利用如上所述的步骤，层叠用于横向MOS晶体管的沟槽内的第一栅电极和第二栅电极，从而减少由蚀刻引起的波动。

公开(公告)号：US08859369B2

公开(公告)日：2014-10-14

申请号：US13761304

申请日：2013-02-07

Applicant: Seiko Instruments Inc.

Inventor： Yukimasa Minami

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7809

Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.

Abstract translation: 提供一种具有垂直MOS晶体管的半导体器件及其制造方法。 垂直MOS晶体管具有沟槽栅极，栅极电极和栅电极下方的N型高浓度掩埋层之间的距离比常规结构形成得更长，并且P型沟槽底面下部区域（5 ）。 以这种方式，当向漏极区域施加高电压并且向栅电极施加0V时，沟槽底表面下部区域（5）被耗尽，从而在断开状态下增加击穿电压。

公开(公告)号：US09704771B2

公开(公告)日：2017-07-11

申请号：US14927040

申请日：2015-10-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yoichi Mimuro ,  Kotaro Watanabe ,  Yukimasa Minami

IPC: H01L23/48 ,  H01L21/336 ,  H01L23/31 ,  H01L21/56 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/3178 ,  H01L21/563 ,  H01L23/562 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00

Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.