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公开(公告)号:US12125884B2
公开(公告)日:2024-10-22
申请号:US18301146
申请日:2023-04-14
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Kevin Kyuheon Cho , Bongyong Lee , Kyeongseok Park , Doojin Choi , Thomas Neyer , Ki Min Kim
CPC classification number: H01L29/1608 , H01L29/1045 , H01L29/66068 , H01L29/66712 , H01L29/7802
Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.
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公开(公告)号:US11658214B2
公开(公告)日:2023-05-23
申请号:US17248160
申请日:2021-01-12
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Kevin Kyuheon Cho , Bongyong Lee , Kyeongseok Park , Doojin Choi , Thomas Neyer , Ki Min Kim
CPC classification number: H01L29/1608 , H01L29/1045 , H01L29/66068 , H01L29/66712 , H01L29/7802
Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.
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公开(公告)号:US11605732B2
公开(公告)日:2023-03-14
申请号:US16675813
申请日:2019-11-06
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Kevin Kyuheon Cho , Bongyong Lee , Kyeongseok Park , Doojin Choi , Thomas Neyer , James Joseph Victory
Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.
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