公开(公告)号：US12125884B2

公开(公告)日：2024-10-22

申请号：US18301146

申请日：2023-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Kyuheon Cho ,  Bongyong Lee ,  Kyeongseok Park ,  Doojin Choi ,  Thomas Neyer ,  Ki Min Kim

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1045 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

公开(公告)号：US11880642B2

公开(公告)日：2024-01-23

申请号：US17930091

申请日：2022-09-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Thomas Neyer ,  YunPeng Xiao ,  Hyeongwoo Jang ,  Peter Dingenen ,  Vaclav Valenta ,  Mehrdad Baghaie Yazdi ,  Christopher Lawrence Rexer ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu ,  Roman Sickaruk

IPC: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

CPC classification number: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F2111/02 ,  G06F2117/12 ,  G06F2119/08

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US11481532B2

公开(公告)日：2022-10-25

申请号：US17076039

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Thomas Neyer ,  YunPeng Xiao ,  Hyeongwoo Jang ,  Peter Dingenen ,  Vaclav Valenta ,  Tirthajyoti Sarkar ,  Mehrdad Baghaie Yazdi ,  Christopher Lawrence Rexer ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu ,  Roman Sickaruk

IPC: G06F30/367 ,  G06F30/31 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US11652027B2

公开(公告)日：2023-05-16

申请号：US17194846

申请日：2021-03-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Thomas Neyer ,  Herbert De Vleeschouwer ,  Fredrik Allerstam

IPC: H01L23/482 ,  H01L21/768 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L23/4824 ,  H01L21/76895 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.

公开(公告)号：US11373859B2

公开(公告)日：2022-06-28

申请号：US17136243

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. Seddon ,  Thomas Neyer ,  Fredrik Allerstam

IPC: H01L21/02

Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.

公开(公告)号：US10665458B2

公开(公告)日：2020-05-26

申请号：US16448540

申请日：2019-06-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. Seddon ,  Thomas Neyer

IPC: H01L21/04 ,  B24B37/20 ,  H01L21/67

Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.

公开(公告)号：US10950596B2

公开(公告)日：2021-03-16

申请号：US16150836

申请日：2018-10-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Xiang Zeng ,  Xiaoli Wu ,  Hao Wang ,  Thomas Neyer ,  Hocheol Jang ,  Sungkyu Song

IPC: H01L27/02 ,  H01L29/06 ,  G01R15/14 ,  G01R19/00 ,  H01L29/861 ,  H01L29/739 ,  G05F1/573 ,  H03K17/14

Abstract: A diode with a current sensor is disclosed. The diode includes an anode region, a cathode region, and a channel-stop region. The diode further includes a sense resistor that is connected between the channel-stop region and the cathode region. When the diode is forward biased, a sense current flows through the sense resistor that corresponds to the forward current flowing through the diode. When the diode is reverse biased, the channel-stop region helps prevent a breakdown condition in the diode.

公开(公告)号：US10896815B2

公开(公告)日：2021-01-19

申请号：US15986403

申请日：2018-05-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. Seddon ,  Thomas Neyer ,  Fredrik Allerstam

IPC: H01L21/02

Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.

公开(公告)号：US11817478B2

公开(公告)日：2023-11-14

申请号：US17247796

申请日：2020-12-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume Roig-Guitart ,  Fredrik Allerstam ,  Thomas Neyer ,  Andrei Konstantinov ,  Martin Domeij ,  Jangkwon Lim

IPC: H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0623 ,  H01L29/1608

Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.

公开(公告)号：US11658214B2

公开(公告)日：2023-05-23

申请号：US17248160

申请日：2021-01-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Kyuheon Cho ,  Bongyong Lee ,  Kyeongseok Park ,  Doojin Choi ,  Thomas Neyer ,  Ki Min Kim

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L29/1045 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.