公开(公告)号：US12169670B2

公开(公告)日：2024-12-17

申请号：US18479179

申请日：2023-10-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Klaus Neumaier ,  YunPeng Xiao ,  Jonathan Harper ,  Vaclav Valenta ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu

IPC: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F111/02 ,  G06F117/12 ,  G06F119/08

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

公开(公告)号：US10755015B2

公开(公告)日：2020-08-25

申请号：US16107158

申请日：2018-08-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Mehrdad Baghaie Yazdi

IPC: G06F30/367 ,  G06F30/39

Abstract: The disclosed embodiments include systems and methods of building an agnostic model of a physically-based semiconductor device. The embodiments may include implementing, in the agnostic model, an arbitrary voltage source in series between a node voltage and a zero value voltage source, implementing, in the agnostic model, a reference capacitor in series between the node voltage and a dummy voltage source, implementing, in the agnostic model, an arbitrary current source between a first node and a second node. The arbitrary current source may include the dummy voltage source divided by the reference capacitor, and the arbitrary current source may model the change in the any property, such as charge, over time within the semiconductor device.

公开(公告)号：US11880642B2

公开(公告)日：2024-01-23

申请号：US17930091

申请日：2022-09-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Thomas Neyer ,  YunPeng Xiao ,  Hyeongwoo Jang ,  Peter Dingenen ,  Vaclav Valenta ,  Mehrdad Baghaie Yazdi ,  Christopher Lawrence Rexer ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu ,  Roman Sickaruk

IPC: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

CPC classification number: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F2111/02 ,  G06F2117/12 ,  G06F2119/08

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US11481532B2

公开(公告)日：2022-10-25

申请号：US17076039

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Thomas Neyer ,  YunPeng Xiao ,  Hyeongwoo Jang ,  Peter Dingenen ,  Vaclav Valenta ,  Tirthajyoti Sarkar ,  Mehrdad Baghaie Yazdi ,  Christopher Lawrence Rexer ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu ,  Roman Sickaruk

IPC: G06F30/367 ,  G06F30/31 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US20190057175A1

公开(公告)日：2019-02-21

申请号：US16107158

申请日：2018-08-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Mehrdad Baghaie Yazdi

IPC: G06F17/50

Abstract: The disclosed embodiments include systems and methods of building an agnostic model of a physically-based semiconductor device. The embodiments may include implementing, in the agnostic model, an arbitrary voltage source in series between a node voltage and a zero value voltage source, implementing, in the agnostic model, a reference capacitor in series between the node voltage and a dummy voltage source, implementing, in the agnostic model, an arbitrary current source between a first node and a second node. The arbitrary current source may include the dummy voltage source divided by the reference capacitor, and the arbitrary current source may model the change in the any property, such as charge, over time within the semiconductor device.

公开(公告)号：US11816405B2

公开(公告)日：2023-11-14

申请号：US17930081

申请日：2022-09-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Klaus Neumaier ,  YunPeng Xiao ,  Jonathan Harper ,  Vaclav Valenta ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu

IPC: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

CPC classification number: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F2111/02 ,  G06F2117/12 ,  G06F2119/08

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

公开(公告)号：US11605732B2

公开(公告)日：2023-03-14

申请号：US16675813

申请日：2019-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Kyuheon Cho ,  Bongyong Lee ,  Kyeongseok Park ,  Doojin Choi ,  Thomas Neyer ,  James Joseph Victory

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16

Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

公开(公告)号：US11481533B2

公开(公告)日：2022-10-25

申请号：US17076072

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Klaus Neumaier ,  YunPeng Xiao ,  Jonathan Harper ,  Vaclav Valenta ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu

IPC: G06F30/31 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.