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    CONCEALED GATE TERMINAL SEMICONDUCTOR PACKAGES AND RELATED METHODS
    1.
    发明申请
    CONCEALED GATE TERMINAL SEMICONDUCTOR PACKAGES AND RELATED METHODS 有权

    公开(公告)号：US20220102248A1

    公开(公告)日：2022-03-31

    申请号：US17305396

    申请日：2021-07-07

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Erwin Ian Vamenta ALMAGRO ,  Maria Clemens Ypil QUINONES ,  Romel N. MANATAD ,  Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG

    IPC: H01L23/495 ,  H01L23/522 ,  H01L23/31

    Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

    MOLDED PACKAGING FOR WIDE BAND GAP SEMICONDUCTOR DEVICES
    3.
    发明申请
    MOLDED PACKAGING FOR WIDE BAND GAP SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220238421A1

    公开(公告)日：2022-07-28

    申请号：US17248382

    申请日：2021-01-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Maria Clemens Ypil QUINONES ,  Bigildis DOSDOS ,  Jerome TEYSSEYRE ,  Erwin Ian Vamenta ALMAGRO ,  Romel N. MANATAD

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.

    ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION
    6.
    发明申请
    ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION 审中-公开

    公开(公告)号：US20190067171A1

    公开(公告)日：2019-02-28

    申请号：US16102922

    申请日：2018-08-14

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Maria Cristina ESTACIO ,  Marlon BARTOLO ,  Maria Clemens Ypil QUINONES ,  Chung-Lin WU

    IPC: H01L23/495 ,  H01L23/00

    Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

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