公开(公告)号：US20250140659A1

公开(公告)日：2025-05-01

申请号：US18941178

申请日：2024-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H10D62/832

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US20240120328A1

公开(公告)日：2024-04-11

申请号：US18542230

申请日：2023-12-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Inpil YOO ,  Jooyang EOM

IPC: H01L25/00 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L23/3677 ,  H01L23/467 ,  H01L23/473 ,  H01L25/072 ,  H01L25/18

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

公开(公告)号：US20220406684A1

公开(公告)日：2022-12-22

申请号：US17664549

申请日：2022-05-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Youngsun KO ,  Seungwon IM ,  Jerome TEYSSEYRE ,  Michael J. SEDDON

IPC: H01L23/44 ,  H05K7/20 ,  H01L21/48

Abstract: Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

公开(公告)号：US20220173022A1

公开(公告)日：2022-06-02

申请号：US17651621

申请日：2022-02-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Seungwon IM ,  JooYang EOM ,  Jerome TEYSSEYRE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

公开(公告)号：US20220059443A1

公开(公告)日：2022-02-24

申请号：US17453623

申请日：2021-11-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Romel MANATAD ,  Chung-Lin WU ,  Bigildis DOSDOS ,  Erwin Ian ALMAGRO ,  Maria Cristina ESTACIO

IPC: H01L23/498 ,  H01L23/495

Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

公开(公告)号：US20220020740A1

公开(公告)日：2022-01-20

申请号：US16948796

申请日：2020-10-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Tiburcio A. MALDO ,  Keunhyuk LEE ,  Jerome TEYSSEYRE

IPC: H01L27/06 ,  H01L23/498 ,  H01L23/13 ,  H01L21/48

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

公开(公告)号：US20240030122A1

公开(公告)日：2024-01-25

申请号：US17813380

申请日：2022-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Jerome TEYSSEYRE

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/367 ,  H01L24/32 ,  H01L24/33 ,  H01L24/29 ,  H01L24/30 ,  H01L23/3735

Abstract: A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.

公开(公告)号：US20230326902A1

公开(公告)日：2023-10-12

申请号：US17658885

申请日：2022-04-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Keunhyuk LEE ,  Jerome TEYSSEYRE ,  Tiburcio A. MALDO

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L24/90

Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

公开(公告)号：US20230230895A1

公开(公告)日：2023-07-20

申请号：US18186842

申请日：2023-03-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Roveendra PAUL ,  Dukyong LEE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/40

CPC classification number: H01L23/3675 ,  H01L23/3735 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2023/4031

Abstract: In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.

公开(公告)号：US20210118774A1

公开(公告)日：2021-04-22

申请号：US16949130

申请日：2020-10-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE ,  Huibin CHEN

IPC: H01L23/492 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.