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    CONCEALED GATE TERMINAL SEMICONDUCTOR PACKAGES AND RELATED METHODS
    5.
    发明申请
    CONCEALED GATE TERMINAL SEMICONDUCTOR PACKAGES AND RELATED METHODS 有权

    公开(公告)号：US20220102248A1

    公开(公告)日：2022-03-31

    申请号：US17305396

    申请日：2021-07-07

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Erwin Ian Vamenta ALMAGRO ,  Maria Clemens Ypil QUINONES ,  Romel N. MANATAD ,  Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG

    IPC: H01L23/495 ,  H01L23/522 ,  H01L23/31

    Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

    VERTICAL AND HORIZONTAL CIRCUIT ASSEMBLIES
    6.
    发明申请
    VERTICAL AND HORIZONTAL CIRCUIT ASSEMBLIES 有权

    公开(公告)号：US20220059443A1

    公开(公告)日：2022-02-24

    申请号：US17453623

    申请日：2021-11-04

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jerome TEYSSEYRE ,  Romel MANATAD ,  Chung-Lin WU ,  Bigildis DOSDOS ,  Erwin Ian ALMAGRO ,  Maria Cristina ESTACIO

    IPC: H01L23/498 ,  H01L23/495

    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

    PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES
    8.
    发明申请
    PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190287886A1

    公开(公告)日：2019-09-19

    申请号：US16429366

    申请日：2019-06-03

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

    IPC: H01L23/495 ,  H01L23/433 ,  H01L23/473 ,  H01L23/00 ,  H01L29/16 ,  H01L21/56 ,  H01L23/373 ,  H01L23/31

    Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.

    ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION
    9.
    发明申请
    ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION 审中-公开

    公开(公告)号：US20190067171A1

    公开(公告)日：2019-02-28

    申请号：US16102922

    申请日：2018-08-14

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Maria Cristina ESTACIO ,  Marlon BARTOLO ,  Maria Clemens Ypil QUINONES ,  Chung-Lin WU

    IPC: H01L23/495 ,  H01L23/00

    Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

    SEMICONDUCTOR DEVICE PACKAGE WITH CLIP INTERCONNECT AND DUAL SIDE COOLING
    10.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE WITH CLIP INTERCONNECT AND DUAL SIDE COOLING 有权

    公开(公告)号：US20210351099A1

    公开(公告)日：2021-11-11

    申请号：US17443230

    申请日：2021-07-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Maria Cristina ESTACIO ,  Elsie Agdon CABAHUG ,  Romel N. MANATAD

    IPC: H01L23/367 ,  H01L23/29 ,  H01L23/495

    Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.

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