公开(公告)号：US20230352518A1

公开(公告)日：2023-11-02

申请号：US18346430

申请日：2023-07-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Rick Carlton JEROME ,  Gordon M. GRIVNA ,  Kevin Alexander STEWART ,  David T. PRICE ,  Jeffrey Peter GAMBINO

IPC: H01C7/00 ,  H01L21/20

CPC classification number: H01L28/24 ,  H01C7/006

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.

公开(公告)号：US20240145504A1

公开(公告)日：2024-05-02

申请号：US18051600

申请日：2022-11-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Rick Carlton JEROME ,  David T. PRICE ,  Michael Gerard KEYES ,  Anne DEIGNAN

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643

Abstract: A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.

公开(公告)号：US20220271118A1

公开(公告)日：2022-08-25

申请号：US17249279

申请日：2021-02-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Rick Carlton JEROME ,  Gordon M. GRIVNA ,  Kevin Alexander STEWART ,  David T. PRICE ,  Jeffrey Peter GAMBINO

IPC: H01L49/02 ,  H01C7/00

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.