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公开(公告)号：US20240266369A1
公开(公告)日：2024-08-08
申请号：US18437410
申请日：2024-02-09
发明人： Atsushi UMEZAKI
IPC分类号： H01L27/12 , G09G3/14 , G09G3/32 , G09G3/36 , G11C19/00 , H01L29/786 , H03B1/00 , H03K3/00 , H03K17/687
CPC分类号： H01L27/1255 , G09G3/14 , G09G3/32 , G09G3/36 , G11C19/00 , H01L29/7869 , H03B1/00 , H03K3/00 , H03K17/6871 , G09G2300/0426 , G09G2310/0286 , G09G2330/021
摘要： Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
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公开(公告)号：US20240153963A1
公开(公告)日：2024-05-09
申请号：US18378206
申请日：2023-10-10
发明人： Atsushi UMEZAKI , Hiroyuki MIYAKE
CPC分类号： H01L27/124 , G09G3/2092 , G09G3/3677 , G11C19/28 , H01L27/0207 , H01L27/1222 , H01L27/1225 , G09G3/3266 , G09G2310/0205 , G09G2310/0248 , G09G2310/061
摘要： To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
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公开(公告)号：US20230352491A1
公开(公告)日：2023-11-02
申请号：US18219831
申请日：2023-07-10
发明人： Atsushi UMEZAKI , Hajime KIMURA
IPC分类号： H01L27/12 , G11C19/28 , G09G3/36 , G09G3/20 , H01L29/786
CPC分类号： H01L27/1225 , G11C19/28 , G09G3/3674 , G09G3/20 , G11C19/287 , G09G3/3677 , H01L27/124 , H01L29/7869 , G09G2310/0286
摘要： An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.
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公开(公告)号：US20230335073A1
公开(公告)日：2023-10-19
申请号：US18212752
申请日：2023-06-22
发明人： Hajime KIMURA , Atsushi UMEZAKI
CPC分类号： G09G3/3648 , G09G3/2096 , G09G3/3677 , G09G3/3688 , G09G2320/0223 , G09G2300/0819 , G09G2300/0814 , G09G2300/0426 , G09G2320/0209 , G09G2320/043
摘要： A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
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公开(公告)号：US20230052898A1
公开(公告)日：2023-02-16
申请号：US17979836
申请日：2022-11-03
发明人： Hajime KIMURA , Atsushi UMEZAKI
摘要： A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
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公开(公告)号：US20220284869A1
公开(公告)日：2022-09-08
申请号：US17747010
申请日：2022-05-18
发明人： Atsushi UMEZAKI
摘要： It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.
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公开(公告)号：US20210350864A1
公开(公告)日：2021-11-11
申请号：US17319156
申请日：2021-05-13
发明人： Atsushi UMEZAKI
IPC分类号： G11C19/18 , H01L29/786 , H01L27/12 , G09G3/3266 , G09G3/36
摘要： A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.
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公开(公告)号：US20210320128A1
公开(公告)日：2021-10-14
申请号：US17177422
申请日：2021-02-17
发明人： Atsushi UMEZAKI , Hiroyuki MIYAKE
摘要： To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
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公开(公告)号：US20210233484A1
公开(公告)日：2021-07-29
申请号：US17153975
申请日：2021-01-21
发明人： Jun KOYAMA , Atsushi UMEZAKI
IPC分类号： G09G3/36 , H03K19/00 , H03K19/0185 , H03K17/687 , H01L27/12 , H01L27/02 , H01L29/786 , G11C19/00
摘要： The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
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公开(公告)号：US20190355303A1
公开(公告)日：2019-11-21
申请号：US16434670
申请日：2019-06-07
发明人： Shunpei YAMAZAKI , Hajime KIMURA , Atsushi UMEZAKI , Yasunori YOSHIDA , Hideaki SHISHIDO , Takuya KIMISHIMA , Yasuyuki ARAI
IPC分类号： G09G3/3233 , G09G3/20 , G09G3/00 , G09G3/3225
摘要： In a display element such as an organic EL element, deterioration progresses due to light emission, and emission luminance is lowered even if the same voltage is applied to the display element. Therefore, use over time causes variations in luminance of each pixel, thereby a so-called “image burn-in” phenomenon occurs. Given this factor, the invention provides a display device which can reduce the difference in deterioration of a display element in each pixel and suppress variations in light emission of a display element in a pixel. It is prevented that only a specific pixel has a long accumulated lighting time. For that purpose, a gray scale of a display pattern is changed to prevent the difference in deterioration of display element in pixels from increasing. Alternatively, a specific display pattern is prevented from being fixedly displayed in a specific region. Further alternatively, a pixel lagging behind in deterioration is deteriorated so that the accumulated lighting time of pixels is equal to each other.
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