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公开(公告)号：US20180074623A1
公开(公告)日：2018-03-15
申请号：US15813809
申请日：2017-11-15
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui XI , Tingting CUI
IPC: G06F3/045 , G06F3/047 , G06F3/041 , G06F3/0354
Abstract: An electronic paper display panel, a touch detecting method thereof and an electronic device are provided. The electronic paper display panel includes: a first substrate and a pixel electrode array which is arranged on the first substrate; an inductance coil array disposed between the first substrate and the pixel electrode array and including a plurality of inductance coils arranged in array, each inductance coil has an input terminal and an output terminal; a plurality of driving lines arranged with the plurality of inductance coils respectively, each driving line is electrically connected to the input terminal of the corresponding inductance coil; and a plurality of touch lines arranged with the plurality of inductance coils respectively, each touch line is electrically connected to the output terminal of the corresponding inductance coil.
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公开(公告)号：US20230137800A1
公开(公告)日：2023-05-04
申请号：US18090918
申请日：2022-12-29
Inventor： Xuhui PENG , Kerui XI , Tingting CUI , Feng QIN , Jie ZHANG
IPC: H01L21/48 , H01L21/56 , H01L23/498 , H01L23/00
Abstract: A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.
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公开(公告)号：US20220285852A1
公开(公告)日：2022-09-08
申请号：US17361356
申请日：2021-06-29
Inventor： Kerui XI , Xuhui PENG , Feng QIN , Tingting CUI , Baiquan LIN
Abstract: Provided are an antenna, a phase shifter, and a communication device. The antenna includes a first metal electrode, a second metal electrode, and a photo-sensitive layer. The first metal electrode and the second metal electrode are respectively located on two opposite sides of the photo-sensitive layer. The first metal electrode includes multiple transmission electrodes. The multiple transmission electrodes are configured to transmit electrical signals. The photo-sensitive layer includes at least one photo-sensitive unit and the at least one photo-sensitive unit overlaps the transmission electrodes. The antenna provides more possibilities for large-scale commercialization.
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公开(公告)号：US20220084973A1
公开(公告)日：2022-03-17
申请号：US17451621
申请日：2021-10-20
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui XI , Feng QIN , Jine LIU , Xiaohe LI , Tingting CUI
Abstract: Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.
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公开(公告)号：US20220293544A1
公开(公告)日：2022-09-15
申请号：US17829619
申请日：2022-06-01
Inventor： Feng QIN , Kerui XI , Tingting CUI , Jie ZHANG , Xuhui PENG
Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.
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Patent Agency Ranking
公开(公告)号：US20200306754A1
公开(公告)日：2020-10-01
申请号：US16444282
申请日：2019-06-18
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui XI , Feng QIN , Jine LIU , Xiaohe LI , Tingting CUI
IPC: B01L3/00
Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M≥4, N≥3, M>N, and A≥2.
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公开(公告)号：US20180067374A1
公开(公告)日：2018-03-08
申请号：US15811680
申请日：2017-11-14
Applicant: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD.
Inventor： Kerui XI , Tingting CUI , Zhaokeng CAO
IPC: G02F1/167 , G02F1/1333 , G06F3/0488 , G02F1/1362
CPC classification number: G02F1/167 , G02F1/13338 , G02F1/136227 , G02F2201/122 , G06F3/0412 , G06F3/044 , G06F3/0488 , G06F2203/04107 , G06F2203/04112 , G09G2300/0439
Abstract: Disclosed are a display panel and a display device. The display panel includes: an upper substrate, a lower substrate and an electrophoretic layer located between the upper substrate and the lower substrate; wherein, the lower substrate includes a plurality of pixel electrodes arranged in a matrix and a plurality of touch electrodes; the upper substrate includes a common electrode layer, a plurality of openings are provided on the common electrode layer, the maximum aperture of the openings is less than or equal to a space between adjacent pixel electrodes.
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公开(公告)号：US20220102406A1
公开(公告)日：2022-03-31
申请号：US17546740
申请日：2021-12-09
Inventor： Kerui XI , Xuhui PENG , Feng QIN , Tingting CUI , Zhenyu JIA
IPC: H01L27/146 , H01L25/16
Abstract: The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.
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公开(公告)号：US20210322981A1
公开(公告)日：2021-10-21
申请号：US17363792
申请日：2021-06-30
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui XI , Feng QIN , Xiangjian KONG , Jiubin ZHOU , Guicai WANG , Yajie WANG , Tingting CUI
Abstract: A panel includes a substrate, an array layer and an electrode array layer. The array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer. The substrate includes drive units arranged in an array, scan line groups, data lines extending in a second direction; and common signal lines extending in the second direction. The scan line group includes first scan lines and second scan lines, extending in a first direction. The first direction is perpendicular with the second direction. The electrode array layer includes drive electrodes arranged in an array; the drive electrodes correspond to the drive units; and the drive unit includes a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor.
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公开(公告)号：US20200316590A1
公开(公告)日：2020-10-08
申请号：US16455013
申请日：2019-06-27
Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.
Inventor： Kerui XI , Feng QIN , Xiangjian KONG , Jiubin ZHOU , Guicai WANG , Yajie WANG , Tingting CUI
IPC: B01L3/00 , H01L27/12 , H03K17/687 , G01N27/22 , G09G3/34
Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal, which are electrically connected with each other. The step-up unit includes a first module, a second module, a third module and a first capacitor, which are electrically connected with each other. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor. The third module is configured to transmit a signal of the third signal input terminal to the second electrode of the first capacitor, which further increases the signal of the first electrode of the first capacitor.
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