公开(公告)号：US11961740B2

公开(公告)日：2024-04-16

申请号：US17516589

申请日：2021-11-01

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Lian Lu ,  Yizheng Zhu ,  Xiangguo Meng

IPC分类号： H01L21/28 ,  H01L21/308 ,  H01L21/67 ,  H01L21/768

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3086 ,  H01L21/67075 ,  H01L21/76802

摘要： The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.

公开(公告)号：US20240055263A1

公开(公告)日：2024-02-15

申请号：US18175092

申请日：2023-02-27

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Lian Lu ,  Yizheng Zhu ,  Kai Qian

IPC分类号： H01L21/304 ,  H01L21/8238

CPC分类号： H01L21/3043 ,  H01L21/823864 ,  H01L21/823857

摘要： A method for manufacturing a sigma-shaped groove in a semiconductor substrate includes: step 1: performing the first etching to form a U-shaped groove in a selected area of the substrate; step 2: performing a second etching configured to expand an opening width of the top sub-groove outward laterally, without changing an opening width of the bottom sub-groove and a depth of the groove; and step 3: performing the third etching which has different etching rates on different crystal surfaces of the semiconductor substrate to further expand the groove into a sigma-shaped groove with a sigma-shaped cross section. An increase of the opening width of the top sub-groove shifts the upper side surface towards an outer side of the sigma-shaped groove, resulting in an upward shift of the apex and reduces a vertical spacing between the apex and top surface of the semiconductor substrate, thereby improving the device performance.

公开(公告)号：US20220139711A1

公开(公告)日：2022-05-05

申请号：US17516589

申请日：2021-11-01

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Lian LU ,  Yizheng Zhu ,  Xiangguo Meng

IPC分类号： H01L21/28 ,  H01L21/308 ,  H01L21/67 ,  H01L21/768

摘要： The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.