公开(公告)号：US20190044018A1

公开(公告)日：2019-02-07

申请号：US15759672

申请日：2016-08-30

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Tokuaki KUNIYOSHI ,  Kenichi HIGASHI ,  Takeshi KAMIKAWA ,  Masatomi HARADA ,  Toshihiko SAKAI ,  Kazuya TSUJINO ,  Liumin ZOU

IPC: H01L31/0747 ,  H01L31/075 ,  H01L31/0224

Abstract: A photovoltaic device and a photovoltaic module are provided that suppressing diffusion of boron and thereby improving conversion efficiency.A photovoltaic device 10 includes: a semiconductor substrate 1; an intrinsic amorphous semiconductor layer 3 provided on the semiconductor substrate 1; n-type amorphous semiconductor strips 4 containing phosphorus as a dopant; and p-type amorphous semiconductor strips 5 containing boron as a dopant, the n- and p-type amorphous semiconductor strips 4 and 5 being provided alternately on the intrinsic amorphous semiconductor layer 3 as viewed along an in-plane direction. Each n-type amorphous semiconductor strip 4 includes a reduced-thickness region TD(n) on a face thereof adjacent to one of the p-type amorphous semiconductor strips 5. Each p-type amorphous semiconductor strip 5 includes a reduced-thickness region TD(p) on a face thereof adjacent to one of the n-type amorphous semiconductor strips 4. The reduced-thickness region TD(p) of the p-type amorphous semiconductor strip 5 has a steeper angle of inclination than does the reduced-thickness region TD(n) of the n-type amorphous semiconductor strip 4.

公开(公告)号：US20170033252A1

公开(公告)日：2017-02-02

申请号：US15302644

申请日：2015-04-03

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masatomi HARADA ,  Toshihiko SAKAI ,  Rihito SUGANUMA ,  Kazuya TSUJINO ,  Tokuaki KUNIYOSHI ,  Takeshi KAMIKAWA

IPC: H01L31/075 ,  H01L31/0376

CPC classification number: H01L31/075 ,  H01L31/022441 ,  H01L31/03762 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: Provided is a photoelectric conversion device capable of suppressing diffusion of a dopant in a p layer or n layer into an adjacent layer. A photoelectric conversion device is provided with a silicon substrate, a substantially intrinsic amorphous layer formed on one surface of the silicon substrate, and a first conductive amorphous layer that is formed on the intrinsic amorphous layer. The first conductive amorphous layer includes a first concentration layer and a second concentration layer that is stacked on the first concentration layer. The dopant concentration of the second concentration layer is 8×1017 cm−3 or more, and is lower than the dopant concentration of the first concentration layer.

Abstract translation: 提供了能够抑制p层或n层中的掺杂剂向相邻层的扩散的光电转换装置。 光电转换装置设置有硅衬底，形成在硅衬底的一个表面上的基本上本征的非晶层以及形成在本征非晶层上的第一导电非晶层。 第一导电非晶层包括层叠在第一浓度层上的第一浓度层和第二浓度层。 第二浓度层的掺杂浓度为8×1017cm-3以上，低于第一浓度层的掺杂浓度。

公开(公告)号：US20220020554A1

公开(公告)日：2022-01-20

申请号：US17367523

申请日：2021-07-05

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kohji SHINKAWA ,  Tadashi IWAMATSU ,  Tomohiro KOSAKA ,  Kazuya TSUJINO ,  Reshan Maduka ABEYSINGHE

IPC: H01J29/96 ,  H01J29/02

Abstract: This electron emitting element includes a lower electrode, a surface electrode facing the lower electrode, a resistance layer arranged between the lower electrode and the surface electrode, and an insulating layer arranged between the lower electrode and the surface electrode. The resistance layer is an insulating resin layer containing conductive fine particles in a dispersed state. The insulating layer has a peripheral region for defining the electron emission region, and an emission control region which is arranged so as to overlap the electron emission region defined by the peripheral region. The emission control region is configured by a line-shaped insulating layer, a plurality of dot-shaped insulating layers, or both a line-shaped insulating layer and a plurality of dot-shaped insulating layers. The percentage of an area that the emission control region represents within an area of an electron emission region defined by the peripheral region is 2% or more and 60% or less.

公开(公告)号：US20150372165A1

公开(公告)日：2015-12-24

申请号：US14767924

申请日：2014-04-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Masatomi HARADA ,  Takeshi KAMIKAWA ,  Kazuya TSUJINO

IPC: H01L31/0236 ,  H01L31/068 ,  H01L31/0376

CPC classification number: H01L31/02363 ,  H01L31/03762 ,  H01L31/068 ,  H01L31/0747 ,  Y02E10/50

Abstract: There is provided a photoelectric converting element in which conversion efficiency increases, by being evenly passivated. The photoelectric converting element is a photoelectric converting element that converts light to electricity, and has a silicon substrate (101) having a textured structure containing plural inclined planes (101a) formed at least on one surface. In a section perpendicular to a line at which two adjacent inclined planes (101a) intersect each other having a concave portion (TXb) of the textured structure interposed therebetween, when a distance between a point Pa at which a tangential line on one of the two inclined planes (101a) and a tangential line of the deepest portion of the concave portion intersect each other and a point Pb at which a tangential line of the other one of the two inclined planes (101a) and a tangential line of the deepest portion of the concave portion intersect each other is a bottom width Lb, the bottom width Lb is 20 nm or greater.

Abstract translation: 提供了通过均匀钝化的转换效率增加的光电转换元件。 光电转换元件是将光转换为光的光电转换元件，并且具有包含形成在至少一个表面上的多个倾斜面（101a）的纹理结构的硅基板（101）。 在垂直于两个相邻的倾斜平面（101a）彼此相交的线的部分中，其间具有纹理结构的凹部（TXb）的截面中，当在两者之一上的切线之间的距离 倾斜平面（101a）和凹部的最深部分的切线相交，并且点Pb在两个倾斜面（101a）中的另一个的切线和最深部分的切线 凹部彼此相交的是底部宽度Lb，底部宽度Lb为20nm以上。

公开(公告)号：US20170170342A1

公开(公告)日：2017-06-15

申请号：US15116926

申请日：2015-01-20

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masatomi HARADA ,  Takeshi KAMIKAWA ,  Kazuya TSUJINO ,  Naoki KOIDE ,  Naoki ASANO ,  Yuta MATSUMOTO

IPC: H01L31/0236 ,  H01L31/0216 ,  H01L31/0747

CPC classification number: H01L31/02363 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/035281 ,  H01L31/0508 ,  H01L31/0516 ,  H01L31/0747 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/547 ,  Y02P70/521

Abstract: There is provided a photoelectric conversion element which includes an n-type single crystal silicon substrate (1). The n-type single crystal silicon substrate (1) includes a central region (11) and an end-portion region (12). The central region (11) is a region which has the same central point as the central point of the n-type single crystal silicon substrate (1) and is surrounded by a circle. The diameter of the circle is set to be a length which is 40% of a length of the shortest side among four sides of the n-type single crystal silicon substrate (1). The central region (11) has a thickness t1. The end-portion region (12) is a region of being within 5 mm from an edge of the n-type single crystal silicon substrate (1). The end-portion region (12) is disposed on an outside of the central region (11) in an in-plane direction of the n-type single crystal silicon substrate (1), and has a thickness t2 which is thinner than the thickness t1. The end-portion region (12) has average surface roughness which is smaller than average surface roughness of the central region (11).