Fanout line structure of array substrate and display panel
    1.
    发明授权
    Fanout line structure of array substrate and display panel 有权
    阵列基板和显示面板的扇出线结构

    公开(公告)号:US09204532B2

    公开(公告)日:2015-12-01

    申请号:US14113582

    申请日:2013-07-31

    Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

    Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部,第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间,第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。

    FANOUT LINE STRUCTURE OF ARRAY SUBSTRATE AND DISPLAY PANEL
    2.
    发明申请
    FANOUT LINE STRUCTURE OF ARRAY SUBSTRATE AND DISPLAY PANEL 有权
    阵列基板和显示面板的FANOUT线结构

    公开(公告)号:US20150009438A1

    公开(公告)日:2015-01-08

    申请号:US14113582

    申请日:2013-07-31

    Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

    Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部,第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间,第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。

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