公开(公告)号：US09960079B2

公开(公告)日：2018-05-01

申请号：US13897202

申请日：2013-05-17

Applicant: Intel Corporation

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/48 ,  H01L23/64 ,  H01L23/66 ,  H05K1/11 ,  H05K1/16 ,  H01L23/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

公开(公告)号：US20170311446A1

公开(公告)日：2017-10-26

申请号：US15253615

申请日：2016-08-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon DODD ,  Roberto BRIOSCHI

IPC: H05K1/18 ,  H05K1/03 ,  H05K3/10 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/181 ,  B81C1/0023 ,  H01L2924/1461 ,  H05K1/0272 ,  H05K1/0293 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/10 ,  H05K3/4007 ,  H05K2201/0175 ,  H05K2201/0338 ,  H05K2201/0391 ,  H05K2201/09727 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2201/10083 ,  H05K2201/10159 ,  H05K2201/10181 ,  H05K2203/171 ,  H05K2203/175

Abstract: The present disclosure is directed to a ceramic substrate that includes a plurality of contact pads, a plurality of electrical traces, and a microelectromechanical die. Contacts on the die are coupled to the plurality of contact pads through the plurality of electrical traces. The substrate also includes a plurality of memory bits formed directly on the substrate. Each memory bit is coupled between a first one of the contact pads and a second one of the contact pads.

公开(公告)号：US09204532B2

公开(公告)日：2015-12-01

申请号：US14113582

申请日：2013-07-31

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Peng Du ,  Ming hung Shih ,  Jiali Jiang

IPC: G02F1/1345 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/025 ,  G02F1/1345 ,  H05K1/0248 ,  H05K1/162 ,  H05K2201/0326 ,  H05K2201/0391 ,  H05K2201/09227 ,  H05K2201/09763 ,  H05K2201/10136

Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.

Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部，第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间，第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。

公开(公告)号：US08575496B2

公开(公告)日：2013-11-05

申请号：US13269079

申请日：2011-10-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。

公开(公告)号：US20130175664A1

公开(公告)日：2013-07-11

申请号：US13735942

申请日：2013-01-07

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: H01F27/40 ,  H01F5/00 ,  H01F27/29 ,  H01F3/00

CPC classification number: H01F27/2804 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01F3/00 ,  H01F5/003 ,  H01F27/24 ,  H01F27/29 ,  H01F27/40 ,  H01F41/041 ,  H01F2027/2809 ,  H01G4/10 ,  H01G4/33 ,  H01L23/64 ,  H01L28/10 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T29/49021

Abstract: A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element.

公开(公告)号：US20120118623A1

公开(公告)日：2012-05-17

申请号：US13359105

申请日：2012-01-26

Applicant: Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

Inventor： Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

IPC: H05K1/16 ,  H01F1/00 ,  B05C5/00 ,  H01B1/14 ,  B32B9/04 ,  B82Y25/00 ,  B82Y30/00

CPC classification number: H05K1/162 ,  H01L2924/0103 ,  H01L2924/01057 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/167 ,  H05K2201/09763

Abstract: A method for forming an embedded passive device module comprises depositing a first amount of an alkali silicate material, co-depositing an amount of embedded passive device material with the amount of alkali silicate material; and thermally processing the amount of alkali silicate material and the amount of embedded passive device material at a temperature sufficient to cure the amount of alkali silicate material and the amount of embedded passive device material and form a substantially moisture free substrate.

Abstract translation: 一种用于形成嵌入式无源器件模块的方法，包括沉积第一量的碱金属硅酸盐材料，将一定量的嵌入的无源器件材料与一定量的碱金属硅酸盐材料共沉积; 并且在足以固化碱金属硅酸盐材料的量和嵌入的无源器件材料的量并形成基本上无水的衬底的温度下热处理碱金属硅酸盐材料的量和嵌入的无源器件材料的量。

公开(公告)号：US08069560B2

公开(公告)日：2011-12-06

申请号：US12708280

申请日：2010-02-18

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01K3/10

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A manufacturing method of a multilayer wiring board that includes a core board, a wiring layer, and an electrically insulating layer that are stacked on the core board. The manufacturing method forms a plurality of through holes in a core member, a thermal expansion coefficient of the core board being between 2 to 20 ppm, and the core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal. The through holes are made conductive by a conductive material, to electrically connect between the front and the back of the core board. A wiring layer and an electrically insulating layer are stacked on one surface of the core board to form a multilayer wiring layer. A capacitor is formed on the other surface of the core board.

Abstract translation: 一种多层布线板的制造方法，其包括堆叠在芯板上的芯板，布线层和电绝缘层。 制造方法在芯部件中形成多个通孔，芯板的热膨胀系数在2〜20ppm之间，并且选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属中的芯构件。 通孔由导电材料制成导电，以电连接芯板的正面和背面。 布线层和电绝缘层堆叠在芯板的一个表面上以形成多层布线层。 电容器形成在芯板的另一个表面上。

公开(公告)号：US20110114376A1

公开(公告)日：2011-05-19

申请号：US12923997

申请日：2010-10-20

Applicant: Mitsuharu Shoji ,  Kiwamu Adachi

Inventor： Mitsuharu Shoji ,  Kiwamu Adachi

IPC: H05K1/16 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/125

Abstract: A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，包括：电容元件形成步骤，将电容元件嵌入到基板内部的基板树脂层内，所述基板包括与介于其间的基板树脂层层叠的多个布线层，所述电容元件形成 包括在所述多个布线层之一上使用导电层形成下电极，或者使用所述多个布线层中的一个布线层; 在等于或低于衬底树脂层的耐热温度或低于室温的温度下形成含结晶金属氧化物的电容器电介质膜; 以及在所述电容器电介质膜的与所述下电极相对的一侧的上表面上形成上电极。

公开(公告)号：US07908744B2

公开(公告)日：2011-03-22

申请号：US12541267

申请日：2009-08-14

Applicant: Shin-Ping Hsu ,  Chih-Kui Yang

Inventor： Shin-Ping Hsu ,  Chih-Kui Yang

IPC: H05K3/36

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09763 ,  H05K2203/0152 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of fabricating a printed circuit board having capacitance components, including: providing a core board having first and second surfaces with first and second wiring layers provided thereon, respectively, and electrically connected, a second dielectric layer, and a carrier board sequentially provided thereon with a second metal layer, a high dielectric material layer, and a third wiring layer with a plurality of first electrode plates thereon; laminating the core board, second dielectric layer, and carrier board to one another; removing the carrier board so as to expose the second metal layer; and patterning the second metal layer so as to form a fifth wiring layer having a plurality of second electrode plates and a plurality of second conductive vias electrically connected to the third wiring layer, thereby allowing the first electrode plates, high dielectric material layer, and second electrode plates together to form a plurality of capacitance components.

Abstract translation: 一种制造具有电容元件的印刷电路板的方法，包括：提供具有分别设置在其上的第一和第二布线层的第一和第二表面的芯板，并且电连接，第二介电层和顺序地设置在其上的载体板 具有第二金属层，高介电材料层和在其上具有多个第一电极板的第三布线层; 将芯板，第二介质层和载体板彼此层叠; 移除载体板以露出第二金属层; 以及图案化所述第二金属层以形成具有多个第二电极板的第五布线层和与所述第三布线层电连接的多个第二导电通孔，从而允许所述第一电极板，高电介质层和第二布线层 电极板一起形成多个电容部件。

公开(公告)号：US20100319970A1

公开(公告)日：2010-12-23

申请号：US12851795

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16 ,  H05K1/00 ,  H05K1/09

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括芯电路板，至少一个电介质层，至少一个嵌入式电容器和至少一个金属层。 核心电路板具有至少一个布线层，并且核心电路板具有连接到布线层的至少一个导电通孔。 至少一个电介质层覆盖布线层，电介质层具有至少一个导电通孔。 至少一个嵌入式电容器嵌入电介质层。 至少一个金属层覆盖电介质层并连接到嵌入式电容器，其中金属层通过导电通孔连接到布线层。