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公开(公告)号：US12113537B1
公开(公告)日：2024-10-08
申请号：US18704562
申请日：2024-01-12
发明人： Nan Li , Haifeng Guo , Zhijun Fan , Lianhua Duan
CPC分类号： H03K5/1508 , H03K3/027 , H03K5/13 , H03K5/15
摘要： The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage clock driving circuit.
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2.发明授权公开(公告)号：US11947889B2
公开(公告)日：2024-04-02
申请号：US18011699
申请日：2022-01-10
发明人： Zhijun Fan , Zuoxing Yang , Nan Li , Wenbo Tian , Weixin Kong
IPC分类号： G06F30/00 , G06F30/327 , G06F30/39 , G06F30/392
CPC分类号： G06F30/392 , G06F30/327 , G06F30/39
摘要： The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.
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公开(公告)号：US11716076B2
公开(公告)日：2023-08-01
申请号：US17602166
申请日：2021-05-13
发明人： Zhijun Fan , Nan Li , Chao Xu , Ke Xue , Zuoxing Yang
CPC分类号： H03K5/135 , G06F9/30047 , G06F9/30101 , H03K3/037 , H04L9/0643
摘要： Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.
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