公开(公告)号：US08103899B2

公开(公告)日：2012-01-24

申请号：US12245203

申请日：2008-10-03

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

公开(公告)号：US20090037767A1

公开(公告)日：2009-02-05

申请号：US12245203

申请日：2008-10-03

申请人： SHIGEMASA SHIOTA ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： SHIGEMASA SHIOTA ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

公开(公告)号：US07231580B2

公开(公告)日：2007-06-12

申请号：US10714982

申请日：2003-11-18

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G11C29/42 ,  G11C29/52 ,  H03M13/29

CPC分类号： G07F7/084 ,  G06F11/1044 ,  G06Q20/341 ,  G07F7/1008

摘要： The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable. If uncorrectable (there are more correction locations than X locations), the control circuit notifies the information processing device that the user data is uncorrectable, and then transfers the user data and the management data to the information processing device.

摘要翻译： 通过在信息存储设备内进行小数据校正并且在信息处理设备中执行主要错误校正，数据的可靠性显着增加，而不会显着增加成本。 当从信息处理装置发出用于传送用于读取的用户数据的请求时，控制电路将用户数据和管理数据传送到检错用户数据的错误检测电路。 如果用户数据不包含错误，则控制电路通知信息处理装置可以传送用户数据，并将其传送到信息处理装置。 如果用户数据包含错误，X计数错误位置和校正数据计算电路使用用户数据和管理数据来计算校正位置和校正数据，并且判断校正位置是否可校正。 如果不可校正（比X位置更多的校正位置），则控制电路向信息处理设备通知用户数据是不可校正的，然后将用户数据和管理数据传送到信息处理设备。

公开(公告)号：US20070038901A1

公开(公告)日：2007-02-15

申请号：US11583156

申请日：2006-10-19

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

公开(公告)号：US20050185449A1

公开(公告)日：2005-08-25

申请号：US11035227

申请日：2005-01-14

申请人： Shigemasa Shiota ,  Kinji Mitani ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Shigemasa Shiota ,  Kinji Mitani ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G06F12/16 ,  G06F3/00 ,  G06F13/00 ,  G11C7/02 ,  G11C7/10 ,  G11C11/00 ,  G11C16/06 ,  H03K5/153 ,  H03K17/30 ,  H03K19/0175

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C16/06

摘要： The present invention is directed to increase noise immunity and largely improve the reliability of a memory device by controlling input/output buffers in accordance with a noise state of input/output signals. When a user data read-transfer request is received from a host, a controller checks the presence or absence of an error in read CRC data. When there is an error in the CRC data due to the influence of noise and the like, a data transfer control unit outputs a control signal to an I/O buffer switching unit to switch I/O buffers to a Schmitt input. If there is no error in the CRC data, the controller transfers user data to the host. When a re-transfer request is sent from the host after the transfer, the controller determines that the data transferred to the host was influenced by noise or the like and the data transfer control unit performs the control of the I/O buffer switching unit to decrease the drivability of the output buffer, thereby reducing noise.

摘要翻译： 本发明旨在通过根据输入/输出信号的噪声状态控制输入/输出缓冲器来提高抗噪声性并大大提高存储器件的可靠性。 当从主机接收到用户数据读取传送请求时，控制器检查读取的CRC数据中是否存在错误。 当由于噪声等的影响而在CRC数据中存在错误时，数据传送控制单元向I / O缓冲器切换单元输出控制信号，以将I / O缓冲器切换到施密特输入。 如果CRC数据中没有错误，则控制器将用户数据传送到主机。 当在传送之后从主机发送再传送请求时，控制器确定传送到主机的数据受到噪声等的影响，并且数据传送控制单元执行I / O缓冲器切换单元的控制 降低输出缓冲器的驾驶性能，从而降低噪音。

公开(公告)号：US07752526B2

公开(公告)日：2010-07-06

申请号：US11747937

申请日：2007-05-14

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G11C29/00

CPC分类号： G07F7/084 ,  G06F11/1044 ,  G06Q20/341 ,  G07F7/1008

摘要： The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable. If uncorrectable (there are more correction locations than X locations), the control circuit notifies the information processing device that the user data is uncorrectable, and then transfers the user data and the management data to the information processing device.

摘要翻译： 通过在信息存储设备内进行小数据校正并且在信息处理设备中执行主要错误校正，数据的可靠性显着增加，而不会显着增加成本。 当从信息处理装置发出用于传送用于读取的用户数据的请求时，控制电路将用户数据和管理数据传送到检错用户数据的错误检测电路。 如果用户数据不包含错误，则控制电路通知信息处理装置可以传送用户数据，并将其传送到信息处理装置。 如果用户数据包含错误，X计数错误位置和校正数据计算电路使用用户数据和管理数据来计算校正位置和校正数据，并且判断校正位置是否可校正。 如果不可校正（比X位置更多的校正位置），则控制电路向信息处理设备通知用户数据是不可校正的，然后将用户数据和管理数据传送到信息处理设备。

公开(公告)号：US07475165B2

公开(公告)日：2009-01-06

申请号：US11058254

申请日：2005-02-16

申请人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G06F13/10

CPC分类号： G11C17/16 ,  G11C16/20

摘要： Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.

摘要翻译： 通过使用相同的控制器来支持外部模拟模块和内部模拟模块，显着减少了半导体数据存储装置的生产成本。 在数据处理系统中，控制器具有由保险丝组成的开关元件。 在由外部电源电路，外部电源监视器电路和时钟发生器元件组成的外部模拟模块之间切换，以及内部电源电路，内部电源监视电路， 激励振荡器电路通过任意断开保险丝来执行。 例如，当将由外部电源监视电路产生的内部电源电压Vdd1提供给控制器等时，熔丝断开。 因此，当使用交错操作时，可以通过例如选择外部模拟模块来根据目的采取措施。

公开(公告)号：US07137027B2

公开(公告)日：2006-11-14

申请号：US10756292

申请日：2004-01-14

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

公开(公告)号：US20050185488A1

公开(公告)日：2005-08-25

申请号：US11058254

申请日：2005-02-16

申请人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G06K19/07 ,  G06F12/00 ,  G11C7/00 ,  G11C16/20 ,  G11C17/16

CPC分类号： G11C17/16 ,  G11C16/20

摘要： Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.

摘要翻译： 通过使用相同的控制器来支持外部模拟模块和内部模拟模块，显着减少了半导体数据存储装置的生产成本。 在数据处理系统中，控制器具有由保险丝组成的开关元件。 在由外部电源电路，外部电源监视器电路和时钟发生器元件组成的外部模拟模块之间切换，以及内部电源电路，内部电源监视电路， 激励振荡器电路通过任意断开保险丝来执行。 例如，当由外部电源监视电路产生的内部电源电压Vdd1被提供给控制器等时，熔断器被断开。 因此，当使用交错操作时，可以通过例如选择外部模拟模块来根据目的采取措施。

公开(公告)号：US07447936B2

公开(公告)日：2008-11-04

申请号：US11583156

申请日：2006-10-19

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。