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公开(公告)号:US20250089168A1
公开(公告)日:2025-03-13
申请号:US18825159
申请日:2024-09-05
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Kensuke UCHIDA
IPC: H05K1/11
Abstract: An interconnect substrate includes a first interconnect layer having a surface, the surface including a first region and a second region, an adhesion enhancing film covering the second region, an insulating layer formed on the adhesion enhancing film, a via hole formed through the insulating layer and the adhesion enhancing film to reach the first region, and a second interconnect layer formed on the insulating layer and in contact with the first region through the via hole, wherein a roughness of the first region is higher than a roughness of the second region.
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公开(公告)号:US20240015888A1
公开(公告)日:2024-01-11
申请号:US18347086
申请日:2023-07-05
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Kensuke UCHIDA
IPC: H05K1/11 , H05K1/02 , H05K3/28 , H01L23/495
CPC classification number: H05K1/115 , H05K1/0298 , H05K3/284 , H01L23/49575 , H05K2203/0574 , H05K2203/049
Abstract: A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, and a second interconnect structure, including a second interconnect layer and a second insulating layer, and disposed on the first interconnect structure. Interconnect width and spacing of the second interconnect layer are smaller than those of the first interconnect layer. The first insulating layer covers a side surface of the first interconnect layer and exposes an upper surface of the first interconnect layer. The second insulating layer covers the upper surface of the first interconnect layer and an upper surface of the first insulating layer. The first insulating layer and the second insulating layer include a filler. An average grain diameter and a maximum grain diameter of the filler included in the second insulating layer are smaller than those of the filler included in the first insulating layer.
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公开(公告)号:US20220157697A1
公开(公告)日:2022-05-19
申请号:US17526089
申请日:2021-11-15
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Hiroshi TANEDA , Kei IMAFUJI , Yoshiki AKIYAMA , Kensuke UCHIDA
IPC: H01L23/498
Abstract: A wiring substrate includes a bendable portion including one or more wiring layers and insulation layers that are alternately stacked. The insulation layers of the bendable portion include a first insulation layer and a second insulation layer. The first insulation layer is located at an inner bent position of the bendable portion when the bendable portion is bent. The second insulation layer is located at an outer bent position of the bendable portion relative to the first insulation layer when the bendable portion is bent. The first insulation layer has a higher elastic modulus than the second insulation layer.
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公开(公告)号:US20240222246A1
公开(公告)日:2024-07-04
申请号:US18542996
申请日:2023-12-18
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Kensuke UCHIDA
IPC: H01L23/498 , H01L21/48 , H01L21/768 , H01L23/00
CPC classification number: H01L23/49822 , H01L21/4867 , H01L21/76877 , H01L23/49816 , H01L24/13 , H01L24/29 , H01L2224/13013 , H01L2224/13025 , H01L2224/29009 , H01L2224/29025 , H01L2924/01029 , H01L2924/014 , H01L2924/15311
Abstract: An interconnect substrate includes an interconnect layer, an insulating layer covering the interconnect layer, an electrode disposed on an upper surface of the interconnect layer and protruding from an upper surface of the insulating layer, and a groove formed in the upper surface of the insulating layer around the electrode, wherein the electrode includes a first portion whose side surface is covered with the insulating layer, a second portion whose entire side surface is located outside the insulating layer, the second portion being partially located inside the groove and partially protruding above the upper surface of the insulating layer, and a metal layer covering both an upper surface of the second portion and the entire side surface of the second portion.
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