公开(公告)号：US20160172241A1

公开(公告)日：2016-06-16

申请号：US15040148

申请日：2016-02-10

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn EBEFORS ,  Henrik KNUTSSON

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/288

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，Ni通过无电解方法选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。