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    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    3.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 有权
    CTE匹配插件及其制作方法

    公开(公告)号：US20150076677A1

    公开(公告)日：2015-03-19

    申请号：US14391855

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Daniel Perttu

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter,

    Abstract translation: 本插入器使得可以在非常宽的范围内调整插入件的热膨胀系数以使其附着的部件相匹配。 半导体插入器包括具有第一侧和相对的第二侧的半导体材料的衬底。 至少有一个导电晶圆通孔包括金属。 至少一个凹部设置在衬底的第一侧中，并且在衬底的半导体材料中，凹槽填充有金属并与晶片通孔连接，从而提供布线结构。 金属填充的通孔和金属填充的凹部的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 晶圆通孔包括窄部分和较宽部分，并且接触元件设置在具有纵横比，高度：直径，<1：1，优选1：1至2：1的布线结构上。

    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE
    4.
    发明申请
    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 有权
    提供通孔和路由结构的方法

    公开(公告)号：US20150054136A1

    公开(公告)日：2015-02-26

    申请号：US14389592

    申请日：2013-03-28

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Daniel Perttu

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76831 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is

    Abstract translation: 提供通孔和布线结构的方法包括：提供具有设置在晶片表面上的凹陷和盲孔的衬底晶片; 在凹槽和孔中提供绝缘层; 对孔和凹槽进行金属化; 并且去除孔的底部中的氧化物层以提供晶片的背侧和前侧之间的接触。 一种半导体器件，包括具有延伸穿过衬底的至少一个金属化通孔的衬底和形成与通孔一起布线的至少一个金属化凹槽。 前侧场和后侧场均有氧化层。 凹槽和通孔中的金属至少在前侧与场上的氧化物齐平，由此提供平坦的前侧。 半导体器件的厚度<300μm。

    ELECTROLESS METAL THROUGH SILICON VIA
    8.
    发明申请
    ELECTROLESS METAL THROUGH SILICON VIA 有权
    电绝缘金属通过硅

    公开(公告)号：US20160172241A1

    公开(公告)日：2016-06-16

    申请号：US15040148

    申请日：2016-02-10

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn EBEFORS ,  Henrik KNUTSSON

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/288

    CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

    Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，Ni通过无电解方法选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。

    Semiconductor devices with close-packed via structures having in-plane routing and method of making same
    10.
    发明授权
    Semiconductor devices with close-packed via structures having in-plane routing and method of making same 有权

    公开(公告)号：US09190356B2

    公开(公告)日：2015-11-17

    申请号：US14384606

    申请日：2013-03-12

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjörn Ebefors ,  Daniel Perttu

    IPC: H01L21/66 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/525

    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

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