公开(公告)号：US20170187481A1

公开(公告)日：2017-06-29

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04J3/14 ,  H04J3/06 ,  H04L7/033 ,  H04L12/24

CPC classification number: H04J3/14 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0331 ,  H04L41/0672

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

公开(公告)号：US20140225653A1

公开(公告)日：2014-08-14

申请号：US13766035

申请日：2013-02-13

Applicant: SILICON LABORATORIES INC.

Inventor： Susumu Hara ,  Adam B. Eldredge ,  Jeffrey S. Batchelor ,  Daniel Gallant

IPC: H03L7/23

CPC classification number: H03L7/235 ,  H03L7/146

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Abstract translation: 级联锁相环（PLL）时钟产生技术降低了保持模式下低抖动时钟信号的频率漂移。 一种装置包括：第一PLL电路，被配置为基于第一时钟信号和第一分频值产生控制信号。 该装置包括：第二PLL电路，被配置为基于低抖动时钟信号和第二分频值产生第一时钟信号。 该装置包括第三PLL电路，其被配置为基于第一时钟信号，第三除法器值和第二时钟信号产生第二除法器值。 低抖动时钟信号可能具有比第二时钟信号更大的温度依赖性，并且第二时钟信号可能具有比低抖动时钟信号更高的抖动。

公开(公告)号：US10320509B2

公开(公告)日：2019-06-11

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04L7/033 ,  H04J3/14 ,  H04L12/24 ,  H04J3/06

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.