公开(公告)号：US09036762B2

公开(公告)日：2015-05-19

申请号：US13864203

申请日：2013-04-16

Applicant: Silicon Laboratories Inc.

Inventor： Brian D. Green

IPC: H03D3/24 ,  H04L7/033

CPC classification number: H04L7/0331 ,  G06F1/10 ,  H03L7/1976 ,  H03L2207/50

Abstract: Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal.

Abstract translation: 公开了涉及产生兼容的时钟信号的技术。 在一个实施例中，一种装置被配置为接收输入时钟信号和参考时钟信号。 在本实施例中，装置包括速率估计单元和锁相环（PLL）单元。 在本实施例中，PLL单元被配置为使用来自速率估计单元的控制信号和输入时钟信号来产生PLL输出时钟信号。 在本实施例中，速率估计单元被配置为调整控制信号，使得PLL输出时钟信号和参考时钟信号是兼容的。 在本实施例中，速率估计单元被配置为基于参考时钟信号和基于PLL输出时钟信号由该装置生成的比较时钟信号来调整控制信号。

公开(公告)号：US09124334B2

公开(公告)日：2015-09-01

申请号：US14283648

申请日：2014-05-21

Applicant: Silicon Laboratories Inc.

Inventor： Javier Elenes ,  Brian D. Green ,  Michael R. May

IPC: H04L27/06 ,  H04B1/08 ,  H04H20/30 ,  H04H60/12 ,  H04L27/00 ,  H04W52/02 ,  H04L25/03

CPC classification number: H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

Abstract: In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

Abstract translation: 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。

公开(公告)号：US20140307842A1

公开(公告)日：2014-10-16

申请号：US13864203

申请日：2013-04-16

Applicant: SILICON LABORATORIES INC.

Inventor： Brian D. Green

IPC: H04L7/033

CPC classification number: H04L7/0331 ,  G06F1/10 ,  H03L7/1976 ,  H03L2207/50

Abstract: Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal.

Abstract translation: 公开了涉及产生兼容的时钟信号的技术。 在一个实施例中，一种装置被配置为接收输入时钟信号和参考时钟信号。 在本实施例中，装置包括速率估计单元和锁相环（PLL）单元。 在本实施例中，PLL单元被配置为使用来自速率估计单元的控制信号和输入时钟信号来产生PLL输出时钟信号。 在本实施例中，速率估计单元被配置为调整控制信号，使得PLL输出时钟信号和参考时钟信号是兼容的。 在本实施例中，速率估计单元被配置为基于参考时钟信号和基于PLL输出时钟信号由该装置产生的比较时钟信号来调整控制信号。

公开(公告)号：US20140254729A1

公开(公告)日：2014-09-11

申请号：US14283648

申请日：2014-05-21

Applicant: Silicon Laboratories Inc.

Inventor： Javier Elenes ,  Brian D. Green ,  Michael R. May

IPC: H04B1/08 ,  H04L25/03

CPC classification number: H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

Abstract: In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

Abstract translation: 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。