公开(公告)号：US09207704B2

公开(公告)日：2015-12-08

申请号：US13662165

申请日：2012-10-26

Applicant: Silicon Laboratories Inc.

Inventor： William J. Anker ,  Srisai R. Seethamraju

IPC: G06F1/08 ,  G06F1/04 ,  H03K5/1252

CPC classification number: G06F1/04 ,  H03K5/1252

Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Abstract translation: 集成电路接收第一和第二时钟信号以及选择时钟信号之一的选择信号。 无毛刺切换电路根据选择信号选择第一和第二时钟中的哪一个提供输出时钟信号。 耦合到无毛刺切换电路的复位电路响应于选择信号的转变方向，响应于转换的第一方向产生第一复位信号，并且响应于转换的第二方向产生第二复位信号 。 复位脉冲分别提供给无毛切换电路中的第一和第二路径，以便在输入时钟之一不存在的情况下复位由第一和第二路径形成的状态机。

公开(公告)号：US09673833B1

公开(公告)日：2017-06-06

申请号：US15196707

申请日：2016-06-29

Applicant: Silicon Laboratories Inc.

Inventor： William J. Anker ,  Timothy A. Monk ,  Rajesh Thirugnanam

IPC: H03M1/10 ,  H03K3/03 ,  H03M1/12 ,  H03M1/56 ,  H03M1/00

CPC classification number: H03M1/1023 ,  H03K3/0315 ,  H03M1/00 ,  H03M1/0624 ,  H03M1/12 ,  H03M1/56 ,  H03M1/60 ,  H03M2201/4233

Abstract: Two sets of information (phase and cycle count) that are created asynchronously in a voltage controlled oscillator based analog-to-digital converter. A third set of information is created that is a delayed cycle count. The three sets of information are used to determine the proper alignment of the phase and the cycle count.

公开(公告)号：US20140118033A1

公开(公告)日：2014-05-01

申请号：US13662165

申请日：2012-10-26

Applicant: SILICON LABORATORIES INC.

Inventor： William J. Anker ,  Srisai R. Seethamraju

IPC: H03L7/00

CPC classification number: G06F1/04 ,  H03K5/1252

Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Abstract translation: 集成电路接收第一和第二时钟信号以及选择时钟信号之一的选择信号。 无毛刺切换电路根据选择信号选择第一和第二时钟中的哪一个提供输出时钟信号。 耦合到无毛刺切换电路的复位电路响应于选择信号的转变方向，响应于转换的第一方向产生第一复位信号，并且响应于转换的第二方向产生第二复位信号 。 复位脉冲分别提供给无毛切换电路中的第一和第二路径，以便在输入时钟之一不存在的情况下复位由第一和第二路径形成的状态机。