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公开(公告)号：US20140068158A1
公开(公告)日：2014-03-06
申请号：US13970779
申请日：2013-08-20
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201 , G06F2212/7204 , G11C16/349 , G11C29/82
Abstract: A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged.
Abstract translation: FLASH存储器用于数据存储，并进一步存储有逻辑到物理地址映射表和写保护映射表。 写保护映射表显示不同逻辑地址的写保护状态。 根据通过来自主机的动态容量管理命令发出的逻辑地址，数据存储设备的控制器修改逻辑到物理地址映射表，以破坏所发布的逻辑地址的逻辑到物理映射关系。 此外，控制器在写保护映射表中将对应于发布的逻辑地址的标志置为写保护模式。 根据写保护映射表的写保护标志量的变化，控制器调整闪存存储器的寿命终止判定值，从而延长闪存的寿命。
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公开(公告)号：US20130326121A1
公开(公告)日：2013-12-05
申请号：US13862816
申请日：2013-04-15
Applicant: SILICON MOTION, INC.
Inventor： Chang-Kai CHENG
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F12/1009 , G06F2212/1008 , G06F2212/152 , G06F2212/2022 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
Abstract: FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.
Abstract translation: FLASH存储器被分配以提供数据存储设备和管理表。 管理表可以以由至少两个级别组成的分级结构记录逻辑到物理地址映射信息。 此外，除了逻辑到物理地址映射信息之外，管理表还可以提供有效页计数表和无效块记录。 在有效页计数表的更新完成之后，逻辑到物理地址映射信息被更新。 无效块记录是基于有效的页面计数表来维护的。
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公开(公告)号：US20160004468A1
公开(公告)日：2016-01-07
申请号：US14851186
申请日：2015-09-11
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG
CPC classification number: G06F12/0246 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F12/1009 , G06F2212/1008 , G06F2212/152 , G06F2212/2022 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
Abstract: A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided.
Abstract translation: 具有分配用于提供数据存储空间的闪速存储器，有效页计数表，逻辑到物理地址映射信息和无效块记录的数据存储设备。 数据存储装置还具有控制器，分配数据存储空间以存储从主机发出的数据，以及建立和维护有效页计数表，逻辑到物理地址映射信息和无效块记录 FLASH存储器来管理数据存储空间。 还提供了一种闪速存储器控制方法。
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公开(公告)号：US20140250258A1
公开(公告)日：2014-09-04
申请号：US14100575
申请日：2013-12-09
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG , Kuan-Yu KE
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F12/0802 , G06F12/0873 , G06F2212/2022 , G06F2212/7203 , G06F2212/7208
Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method. The control method includes the following steps: dividing a plurality of blocks of the FLASH memory into groups to be accessed via different channels; allocating at least one set of cache spaces in a random access memory for temporary write data storage for the different channels; separating write data issued from a host to correspond to the plurality of channels; and, when data arrangement for every channel has been completed in one set of cache spaces, writing the data that has been arranged in the set of cache spaces to the FLASH memory via the plurality of channels corresponding to the different cache spaces of the set of cache spaces.
Abstract translation: 具有通过多个通道访问的FLASH存储器和FLASH存储器控制方法的数据存储设备。 该控制方法包括以下步骤：将FLASH存储器的多个块划分成不同通道要访问的组; 在随机存取存储器中分配至少一组高速缓存空间用于不同信道的临时写数据存储; 将从主机发出的对应于所述多个信道的写入数据分离; 并且当在一组高速缓存空间中完成每个信道的数据排列时，通过与该组高速缓存空间中的不同高速缓存空间对应的多个信道将已经排列在该组高速缓存空间中的数据写入到FLASH存储器 缓存空间。
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公开(公告)号：US20140078825A1
公开(公告)日：2014-03-20
申请号：US13966554
申请日：2013-08-14
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG
IPC: G11C16/16
CPC classification number: G11C16/16 , G06F12/0246 , G06F12/06 , G06F2212/1016 , G06F2212/7208 , G06F2212/7211
Abstract: Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module. The controller erases at least one Xblock for space release and moves data on Xblocks for wear leveling.
Abstract translation: 公开了存储空间分配和用于闪速存储器模块的损耗均衡技术。 闪存模块包括多个闪存芯片。 用于FLASH存储器模块的控制器将FLASH存储器模块的存储空间划分为用于管理FLASH存储器模块的Xblock。 控制器至少擦除一个Xblock以释放空间，并移动Xblock上的数据进行磨损均衡。
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Patent Agency Ranking
公开(公告)号：US20170364277A1
公开(公告)日：2017-12-21
申请号：US15618232
申请日：2017-06-09
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG , Yu-Chih LIN
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/00
Abstract: The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.
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公开(公告)号：US20170344423A1
公开(公告)日：2017-11-30
申请号：US15675817
申请日：2017-08-14
Applicant: Silicon Motion, Inc.
Inventor： Li-Shuo HSIAO , Chang-Kai CHENG
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1016 , G06F12/00 , G06F12/0246 , G06F2212/1016 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.
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公开(公告)号：US20140379964A1
公开(公告)日：2014-12-25
申请号：US14302692
申请日：2014-06-12
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block.
Abstract translation: 提供数据存储装置。 耦合到主机的数据存储设备包括：闪速存储器; 以及控制器，被配置为控制所述闪存的访问; 其中当所述主机执行对所述闪速存储器的随机数据访问时，所述控制器基于全局映射表检索与要读取的第一数据相关联的所述闪速存储器中的相应块和对应页的地址信息，并且预取相应的 基于地址信息从闪存读取页面; 其中，当所述控制器获取所述地址信息时，所述控制器还基于本地映射表来确定所述第一数据是否位于当前缓冲块中; 其中，当所述第一数据位于所述当前缓冲块中时，所述控制器进一步取消所述预取的对应页面，并且从当前缓冲块读取所述第一数据。
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公开(公告)号：US20130326120A1
公开(公告)日：2013-12-05
申请号：US13862782
申请日：2013-04-15
Applicant: SILICON MOTION, INC.
Inventor： Chang-Kai CHENG
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7202
Abstract: A data storage device and operating method for a FLASH memory are disclosed. The data storage device includes a FLASH memory and a controller. The FLASH memory includes a first block and a second block. The first and second blocks each includes a plurality of pages. The controller executes a firmware to determine whether a data segment from a host is a complete page segment. When the data segment is a complete page segment, the controller stores the data segment into the first block. When the data segment is an incomplete page segment, the controller stores the data into segment the second block.
Abstract translation: 公开了一种用于闪速存储器的数据存储装置和操作方法。 数据存储装置包括闪速存储器和控制器。 闪存存储器包括第一块和第二块。 第一和第二块各自包括多个页面。 控制器执行固件以确定来自主机的数据段是否是完整的页面段。 当数据段是完整的页面段时，控制器将数据段存储到第一个块中。 当数据段是不完整的页面段时，控制器将数据存储在第二个块中。
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公开(公告)号：US20180107405A1
公开(公告)日：2018-04-19
申请号：US15844890
申请日：2017-12-18
Applicant: Silicon Motion, Inc.
Inventor： Chang-Kai CHENG , Yu-Chih LIN
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/00
Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.
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