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公开(公告)号：US20130076401A1
公开(公告)日：2013-03-28
申请号：US13680239
申请日：2012-11-19
Applicant: SK HYNIX INC.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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公开(公告)号：US09148098B2
公开(公告)日：2015-09-29
申请号：US14027824
申请日：2013-09-16
Applicant: SK hynix Inc.
Inventor： Hyung-Soo Kim
CPC classification number: H03F3/45188 , H03F1/303 , H03F3/45183 , H03F3/45475 , H03F2203/45318 , H03F2203/45396 , H03F2203/45562 , H03F2203/45616
Abstract: A differential amplifier circuit includes a differential amplification unit suitable for amplifying difference between signals of an input terminal and a complementary input terminal, receiving the same voltage level through the input terminal and the complementary input terminal at a measurement period, and receiving an input signal and a complementary input signal through the input terminal and the complementary input terminal, respectively, at an operation period, an offset control unit suitable for generating offset information using an output of the differential amplification unit at the measurement period, and an offset compensation unit suitable for compensating for an offset of the differential amplification unit in response to the offset information.
Abstract translation: 差分放大器电路包括适于放大输入端子和互补输入端子的信号之间的差异的差分放大单元，在测量周期通过输入端子和互补输入端子接收相同的电压电平，以及接收输入信号和 在操作周期分别通过输入端和互补输入端的互补输入信号，适于在测量周期使用差分放大单元的输出产生偏移信息的偏移控制单元和适于 响应于偏移信息补偿差分放大单元的偏移。
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公开(公告)号：US08461878B2
公开(公告)日：2013-06-11
申请号：US13680239
申请日：2012-11-19
Applicant: SK Hynix Inc.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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