公开(公告)号：US20130076401A1

公开(公告)日：2013-03-28

申请号：US13680239

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03K5/153

CPC classification number: H03K5/153

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

公开(公告)号：US08461878B2

公开(公告)日：2013-06-11

申请号：US13680239

申请日：2012-11-19

Applicant: SK Hynix Inc.

Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03K5/153

CPC classification number: H03K5/153

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

公开(公告)号：US09276500B2

公开(公告)日：2016-03-01

申请号：US14106792

申请日：2013-12-15

Applicant: SK hynix Inc.

Inventor： Boo-Ho Jung ,  Sung-Woo Han ,  Ic-Su Oh ,  Jun-Ho Lee ,  Hyun-Seok Kim ,  Sun-Ki Cho ,  Tae-Hoon Kim ,  Ki-Chul Hong

IPC: G11C11/401 ,  H02M11/00 ,  G11C5/06 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

CPC classification number: H02M11/00 ,  G11C5/063 ,  G11C5/14 ,  G11C7/02 ,  G11C11/4074

Abstract: A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

Abstract translation: 蓄电池电容器包括具有两个或更多个电容器的第一电容器组，其在第一电源电压端子和第二电源电压端子之间彼此串联耦合，第二电容器组具有两个或更多个电容器，其串联耦合 在第三电源电压端子与第四电源电压端子之间相互连接的第二电容器组和适于将第一电容器组的电容器之间的第一耦合节点电耦合到第二电容器组的电容器之间的第二耦合节点的连接线 。