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    Data sense amplification circuit and semiconductor memory device including the same
    2.
    发明授权
    Data sense amplification circuit and semiconductor memory device including the same 有权

    公开(公告)号：US09947385B1

    公开(公告)日：2018-04-17

    申请号：US15589056

    申请日：2017-05-08

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C7/06

    CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

    Abstract: A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells.

    Majority decision circuit
    3.
    发明授权
    Majority decision circuit 有权
    多数决策电路

    公开(公告)号：US09054697B2

    公开(公告)日：2015-06-09

    申请号：US13890802

    申请日：2013-05-09

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    IPC: H03K19/23 ,  H03K19/003 ,  H03K19/08

    CPC classification number: H03K19/0813 ,  H03K19/23

    Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

    Abstract translation: 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段

    Duty cycle correction circuit and operation method thereof
    4.
    发明授权
    Duty cycle correction circuit and operation method thereof 有权
    占空比校正电路及其操作方法

    公开(公告)号：US09018994B2

    公开(公告)日：2015-04-28

    申请号：US13844928

    申请日：2013-03-16

    Applicant: SK Hynix Inc.

    Inventor： Shin-Deok Kang ,  Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

    IPC: H03K5/04 ,  H03K5/156

    CPC classification number: H03K3/017 ,  H03K5/1565

    Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

    Abstract translation: 占空比校正电路包括：时钟调整单元，被配置为响应于占空比控制信号调整输入时钟信号的占空比并产生输出时钟信号;跟踪类型设置单元，被配置为产生用于设置的跟踪类型选择信号 基于输出时钟信号的占空比锁定状态的第一或第二跟踪类型，以及控制信号生成单元，被配置为响应于跟踪类型选择生成并入第一或第二跟踪类型的占空比控制信号 信号和输出时钟信号。

    Memory device correcting data error of weak cell
    5.
    发明授权
    Memory device correcting data error of weak cell 有权

    公开(公告)号：US10229752B2

    公开(公告)日：2019-03-12

    申请号：US15682685

    申请日：2017-08-22

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi ,  Sung-Soo Chi ,  Dong-Jae Lee

    IPC: G11C7/00 ,  G11C29/00 ,  G11C29/42 ,  G11C29/50

    Abstract: A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.

    Clock generation circuit
    6.
    发明授权
    Clock generation circuit 有权

    公开(公告)号：US10079606B2

    公开(公告)日：2018-09-18

    申请号：US14793451

    申请日：2015-07-07

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Dae-Han Kwon ,  Shin-Deok Kang

    IPC: H03D3/24 ,  H03K23/66 ,  G06F1/04

    CPC classification number: H03K23/662 ,  G06F1/04

    Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

    Latch circuit
    7.
    发明授权
    Latch circuit 有权
    锁存电路

    公开(公告)号：US09397642B2

    公开(公告)日：2016-07-19

    申请号：US14678704

    申请日：2015-04-03

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi ,  Mi-Hyun Hwang

    IPC: H03K3/356

    CPC classification number: H03K3/356147 ,  H03K3/356104 ,  H03K3/356182

    Abstract: A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.

    Abstract translation: 锁存电路包括：第一PMOS晶体管，其适于基于第一节点的电压上拉驱动第二节点;第一NMOS晶体管，其适于基于第一节点的电压下拉驱动第二节点;第二NMOS晶体管， PMOS晶体管，其适于基于第二节点的电压上拉驱动第一节点;第二NMOS晶体管，适于基于第二节点的电压来下拉驱动第一节点;第一分离元件，适于电分离 当第一PMOS晶体管导通时来自第二节点的第一NMOS晶体管，以及适于在第二PMOS晶体管导通时将第二NMOS晶体管与第一节点电分离的第二分离元件。

    Semiconductor device and method for driving the same
    8.
    发明授权
    Semiconductor device and method for driving the same 有权
    半导体装置及其驱动方法

    公开(公告)号：US09361969B2

    公开(公告)日：2016-06-07

    申请号：US14278031

    申请日：2014-05-15

    Applicant: SK hynix Inc.

    Inventor： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC: G11C7/04 ,  G11C11/406

    CPC classification number: G11C11/40626

    Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.

    Abstract translation: 一种半导体器件包括周期性信号发生电路，用于响应于作为默认值的第一微调信号产生具有设定周期而不管温度变化的周期信号，并且响应于该温度控制周期信号的设定周期 第二微调信号和内部电路，以响应周期信号执行设定操作。

    Duty cycle correction circuit and operation method thereof
    9.
    发明授权
    Duty cycle correction circuit and operation method thereof 有权

    公开(公告)号：US09257968B2

    公开(公告)日：2016-02-09

    申请号：US14668542

    申请日：2015-03-25

    Applicant: SK hynix Inc.

    Inventor： Shin-Deok Kang ,  Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

    IPC: H03K3/017 ,  H03K5/156

    CPC classification number: H03K3/017 ,  H03K5/1565

    Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

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