公开(公告)号：US20240185929A1

公开(公告)日：2024-06-06

申请号：US18325730

申请日：2023-05-30

Applicant: SK hynix Inc.

Inventor： Hyeok Chan SOHN ,  Beom Ju SHIN ,  Byung Ryul KIM ,  Kang Wook JO

IPC: G11C16/26 ,  G11C16/12

CPC classification number: G11C16/26 ,  G11C16/12

Abstract: The present technology relates to an electronic device. A memory device according to the present technology may include a first plane, a second plane, a data input/output circuit, and an encoder. The data input/output circuit may output data read from the first and second planes. The encoder may compress second data read from the second plane while first data read from the first plane is being output. The data input/output circuit may output the compressed second data after outputting the first data.

公开(公告)号：US20230070958A1

公开(公告)日：2023-03-09

申请号：US17671043

申请日：2022-02-14

Applicant: SK hynix Inc.

Inventor： Tae Hee YOU ,  Beom Ju SHIN

IPC: G11C7/10

Abstract: A memory system includes at least one memory die and a controller coupled to the at least one memory die via a data path. The at least one memory die includes plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes. The controller transfers a first status check command to the at least one memory die and receives a first response including the operation statuses and the operation results regarding the respective memory planes.

公开(公告)号：US20230289083A1

公开(公告)日：2023-09-14

申请号：US17864094

申请日：2022-07-13

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN ,  Tae Hee YOU

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/061 ,  G06F3/0679

Abstract: A memory device may include: a plurality of planes, each suitable for inputting/outputting data in units of pages, a latch suitable for performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, among the plurality of planes, and storing the received data, and a logic controller suitable for comparing first plane information, corresponding to the data that is stored in the latch, to second plane information, corresponding to an output command that is received after the read command is received, in response to the output command, and suitable for selectively outputting the data of the latch.

公开(公告)号：US20190324647A1

公开(公告)日：2019-10-24

申请号：US16460540

申请日：2019-07-02

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN

IPC: G06F3/06

Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at least one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.

公开(公告)号：US20190295655A1

公开(公告)日：2019-09-26

申请号：US16162772

申请日：2018-10-17

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN

IPC: G11C16/10 ,  G11C16/26 ,  G06F3/06

Abstract: A storage device may perform a reprogram operation on a page on which a program operation is interrupted due to a sudden power off. The storage device may include a memory device including a plurality of memory blocks, each of which includes a plurality of pages, and a memory controller configured to perform a reprogram operation on a page in which a program operation is suspended using reprogram data that is set depending on threshold voltages of memory cells included in the page on which the program operation is interrupted, among the plurality of pages.

公开(公告)号：US20180196620A1

公开(公告)日：2018-07-12

申请号：US15613679

申请日：2017-06-05

Applicant: SK hynix Inc.

Inventor： Jin Pyo KIM ,  Beom Ju SHIN

IPC: G06F3/06 ,  G11C29/50

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A data storage device includes a plurality of nonvolatile memory devices; and a controller suitable for determining a write sequence for the nonvolatile memory devices, based on respective write times of the nonvolatile memory devices, and transmitting write commands sequentially in an interleaving manner to the nonvolatile memory devices according to the write sequence.

公开(公告)号：US20180011635A1

公开(公告)日：2018-01-11

申请号：US15366467

申请日：2016-12-01

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/068

Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.

公开(公告)号：US20230126507A1

公开(公告)日：2023-04-27

申请号：US17682602

申请日：2022-02-28

Applicant: SK hynix Inc.

Inventor： Sung Hun KIM ,  Beom Ju SHIN

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F1/30 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

公开(公告)号：US20210210148A1

公开(公告)日：2021-07-08

申请号：US17210732

申请日：2021-03-24

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN

IPC: G11C16/26 ,  G11C7/10 ,  G11C16/14 ,  G11C16/12

Abstract: There are provided a memory system and an operating method thereof. The memory system includes a semiconductor memory configured to perform a memory operation and perform a suspend operation of suspending a currently performed memory operation and a controller configured to control the memory operation. The controller controls the semiconductor memory to perform the suspend operation in a suspension-allowed period by determining a detailed operation period of the currently performed memory operation.

公开(公告)号：US20210072922A1

公开(公告)日：2021-03-11

申请号：US16821749

申请日：2020-03-17

Applicant: SK hynix Inc.

Inventor： Beom Ju SHIN ,  Yun Jung YEOM

IPC: G06F3/06 ,  G06F9/48

Abstract: A memory controller for controlling a memory device for storing data, the memory controller, the memory controller comprising: a request transmitter for providing a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation and a command controller for generating and outputting a program suspend command, based on the program suspend request, and outputting a cache read command or normal read command, based on a number of commands corresponding to a request received from the host, which are queued in a command queue.