公开(公告)号：US20170294581A1

公开(公告)日：2017-10-12

申请号：US15634573

申请日：2017-06-27

Applicant: SK hynix Inc.

Inventor： Gyu Hyun KIM ,  Dae Won KIM ,  Byoung Ki LEE ,  Han Woo CHO

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

公开(公告)号：US20160359111A1

公开(公告)日：2016-12-08

申请号：US14883216

申请日：2015-10-14

Applicant: SK hynix Inc.

Inventor： Gyu Hyun KIM ,  Dae Won KIM ,  Byoung Ki LEE ,  Han Woo CHO

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract translation: 一种半导体器件制造方法，包括在电阻式存储器层上依次形成界面导电层和蚀刻停止层; 在所述蚀刻停止层上形成主导电层; 通过图案化主导电层来暴露蚀刻停止层的一部分; 通过对蚀刻停止层的部分进行构图来暴露界面导电层的一部分; 通过图案化界面导电层的一部分形成上电极结构; 清洁上电极结构的表面和电阻性存储层的暴露表面; 以及使用上电极结构作为蚀刻掩模来构图电阻存储层。

公开(公告)号：US20170104154A1

公开(公告)日：2017-04-13

申请号：US14988868

申请日：2016-01-06

Applicant: SK hynix Inc.

Inventor： Hyung Keun KIM ,  Byoung Ki LEE ,  Su Jin CHAE

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2454 ,  H01L45/1206 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

Abstract: A variable resistive memory device may include a phase change region, a phase change layer, a gap-filling layer and an upper electrode. The phase change region may have a sidewall and a bottom surface. The phase change layer may have a linear shape extended along the bottom surface and the sidewall of the phase change region. The gap-filling layer may be formed in a portion of the phase change region surrounded by the phase change layer. The upper electrode may be formed on the phase change layer and the gap-filling layer.