公开(公告)号：US20170373041A1

公开(公告)日：2017-12-28

申请号：US15405619

申请日：2017-01-13

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM ,  Jong Hoon KIM ,  Dae Won KIM ,  Hyeong Seok CHOI

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

公开(公告)号：US20240105652A1

公开(公告)日：2024-03-28

申请号：US18097931

申请日：2023-01-17

Applicant: SK hynix Inc.

Inventor： Dae Won KIM ,  Sung Kyu KIM

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1111 ,  H01L2224/11474 ,  H01L2224/13017 ,  H01L2224/13147

Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist layer on a substrate and forming a second photoresist layer on the first photoresist layer. The method also includes forming a first dissolvable region having a first width in the first photoresist layer and a second dissolvable region having a second width different from the first width in the second photoresist layer by radiating exposure light to some parts of the second and first photoresist layer. The method further includes forming a second opening in the second photoresist layer and a first opening in the first photoresist layer by developing the second dissolvable region and the first dissolvable region. The method additionally includes forming a conductive bump that fills the first and second openings.

公开(公告)号：US20240074165A1

公开(公告)日：2024-02-29

申请号：US18194654

申请日：2023-04-03

Applicant: SK hynix Inc.

Inventor： Dae Won KIM ,  Yu Ri KIM ,  Tae Kyun KIM ,  Jin Hwan JEON ,  Dong Goo CHOI ,  Ri CHOI

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device comprises a substrate including first and second regions; a plurality of conductive line structures disposed over the substrate; a plurality of conductive contact plugs formed between the conductive line structures disposed over the first region of the substrate; and a plurality of dummy dielectric plugs disposed over the second region of the substrate.

公开(公告)号：US20220406789A1

公开(公告)日：2022-12-22

申请号：US17562838

申请日：2021-12-27

Applicant: SK hynix Inc.

Inventor： Jin Hwan JEON ,  Dae Won KIM ,  Tae Kyun KIM ,  Jung Woo PARK ,  Sung Hwan AHN ,  Su Ock CHUNG ,  Dong Goo CHOI

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/308

Abstract: Present invention is related to a semiconductor device with an improved reliability and a method for the same. A method for fabricating a semiconductor device according to an embodiment of the present invention may comprise: forming a plurality of bit line structures over a substrate; forming line-shaped openings between the bit line structures; forming a stopper structure on edges of the line-shaped openings; filling a line pattern in each of the line-shaped openings; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line patterns; and filling a plug isolation layer in the isolation grooves.

公开(公告)号：US20220352323A1

公开(公告)日：2022-11-03

申请号：US17549328

申请日：2021-12-13

Applicant: SK hynix Inc.

Inventor： Dae Won KIM ,  Tae Kyun KIM ,  Dong Goo CHOI

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.

公开(公告)号：US20170294581A1

公开(公告)日：2017-10-12

申请号：US15634573

申请日：2017-06-27

Applicant: SK hynix Inc.

Inventor： Gyu Hyun KIM ,  Dae Won KIM ,  Byoung Ki LEE ,  Han Woo CHO

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

公开(公告)号：US20160359111A1

公开(公告)日：2016-12-08

申请号：US14883216

申请日：2015-10-14

Applicant: SK hynix Inc.

Inventor： Gyu Hyun KIM ,  Dae Won KIM ,  Byoung Ki LEE ,  Han Woo CHO

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Abstract translation: 一种半导体器件制造方法，包括在电阻式存储器层上依次形成界面导电层和蚀刻停止层; 在所述蚀刻停止层上形成主导电层; 通过图案化主导电层来暴露蚀刻停止层的一部分; 通过对蚀刻停止层的部分进行构图来暴露界面导电层的一部分; 通过图案化界面导电层的一部分形成上电极结构; 清洁上电极结构的表面和电阻性存储层的暴露表面; 以及使用上电极结构作为蚀刻掩模来构图电阻存储层。