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公开(公告)号：US11227664B2
公开(公告)日：2022-01-18
申请号：US17009128
申请日：2020-09-01
申请人： SK hynix Inc.
发明人： Hyun Chul Cho
摘要： Provided herein is a memory device and a method of operating the same. The memory device may include a memory block, a voltage generation circuit configured to operate in a first mode in which an operating voltage is generated using an internal voltage or a second mode in which the operating voltage is generated using an external voltage, and to provide the operating voltage to the memory block, and a control logic configured to measure and store a first rising time during which the operating voltage rises to a target level in the first mode, and to control the voltage generation circuit so that a second rising time during which the operating voltage rises to the target level in the second mode is equal to or longer than the first rising time.
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公开(公告)号：US12020757B2
公开(公告)日：2024-06-25
申请号：US17550234
申请日：2021-12-14
申请人： SK hynix Inc.
发明人： Won Jae Choi , Min Su Kim , Hyun Chul Cho
CPC分类号： G11C16/32 , G11C16/102 , G11C16/14 , G11C16/26 , G11C16/30
摘要： A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.
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3.发明授权公开(公告)号：US11081146B2
公开(公告)日：2021-08-03
申请号：US16670795
申请日：2019-10-31
申请人： SK hynix Inc.
发明人： Hyun Chul Cho
摘要： The present disclosure relates to method of operating a memory device, the memory device includes a memory cell array, a voltage generator, and control logic. The voltage generator configured to increase a power supply voltage. The control logic is configured to store a time based on the increased power supply voltage and a reference voltage. The reference voltage is a voltage level used to perform an operation on the memory cell array.
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公开(公告)号：US11309038B2
公开(公告)日：2022-04-19
申请号：US16996213
申请日：2020-08-18
申请人： SK hynix Inc.
发明人： Hyun Chul Cho
摘要： A memory device may include: a memory cell array including a plurality of planes; and a voltage generation circuit including a master pump component and at least one or more sub-pump components that respectively correspond to the planes. During an interleaved operation, the master pump component may generate a first output voltage in response to a first pump clock, and the sub-pump components may generate second output voltages in response to second pump clocks. The master pump component and the sub-pump components may respectively provide the first output voltage and the second output voltages to the corresponding planes. During a non-interleaved operation, the master pump component and the sub-pump components may generate the first output voltage in response to the first pump clock and provide the first output voltage to a selected plane of the plurality of planes.
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公开(公告)号：US11205486B2
公开(公告)日：2021-12-21
申请号：US17064261
申请日：2020-10-06
申请人： SK hynix Inc.
发明人： Won Jae Choi , Hyun Chul Cho
摘要： The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.
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