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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200160904A1

    公开(公告)日：2020-05-21

    申请号：US16751427

    申请日：2020-01-24

    Applicant: SK hynix Inc.

    Inventor： Jae-Seung LEE ,  No-Geun JOO

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

    TEST SETTING CIRCUIT, SEMICONDUCTOR DEVICE, AND TEST SETTING METHOD
    3.
    发明申请
    TEST SETTING CIRCUIT, SEMICONDUCTOR DEVICE, AND TEST SETTING METHOD 有权
    测试设置电路，半导体器件和测试设置方法

    公开(公告)号：US20160139203A1

    公开(公告)日：2016-05-19

    申请号：US14689944

    申请日：2015-04-17

    Applicant: SK hynix Inc.

    Inventor： Jae-Seung LEE ,  Choung-Ki SONG

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31701 ,  G01R31/2601 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31703

    Abstract: A test setting circuit includes a first detection unit suitable for detecting whether a first code is sequentially inputted based on a first sequence, at each of first to Nth steps, where N is a natural number; a second detection unit suitable for sequentially receiving a second code through the first to Nth steps, and detecting whether the second code that is sequentially inputted through the first to Nth steps has a value corresponding to a second sequence; and a test setting unit suitable for setting a test mode when it is detected that the first code and the second code are inputted to satisfy the first sequence and the second sequence.

    Abstract translation: 测试设置电路包括：第一检测单元，适于在第一至第N步骤中的每一个步骤中检测第一代码是否基于第一序列顺序地输入，其中N是自然数; 第二检测单元，适于通过第一至第N步骤顺序地接收第二代码，并且检测通过第一至第N步骤顺序输入的第二代码是否具有对应于第二序列的值; 以及测试设置单元，其适于在检测到第一代码和第二代码被输入时设置测试模式以满足第一序列和第二序列。

    LATCH CIRCUIT AND LATCH CIRCUIT ARRAY INCLUDING THE SAME
    4.
    发明申请
    LATCH CIRCUIT AND LATCH CIRCUIT ARRAY INCLUDING THE SAME 有权
    锁定电路和锁存电路包括相同的阵列

    公开(公告)号：US20160118963A1

    公开(公告)日：2016-04-28

    申请号：US14569440

    申请日：2014-12-12

    Applicant: SK hynix Inc.

    Inventor： Jae-Seung LEE

    IPC: H03K3/356

    CPC classification number: H03K3/356104

    Abstract: A latch circuit may include: first to Nth storage nodes where N is an even number equal to or more than four; first to Nth pairs of transistors each including a PMOS transistor and an NMOS transistor which are coupled in series through a corresponding storage node among the first to Nth storage nodes, wherein each of the first to Nth storage nodes is coupled to a gate of the NMOS transistor of the transistor pair at the previous stage and a gate of the PMOS transistor of the transistor pair at the next stage; first to Nth PMOS transistors suitable for driving corresponding storage nodes among the first to Nth storage nodes to a high level; and first to Nth NMOS transistors suitable for driving corresponding storage nodes among the first to Nth storage nodes to a low level.

    Abstract translation: 锁存电路可以包括：第一到第N个存储节点，其中N是等于或大于4的偶数; 第一至第N对晶体管，每个晶体管包括通过第一至第N存储节点中的对应存储节点串联耦合的PMOS晶体管和NMOS晶体管，其中第一至第N存储节点中的每一个耦合到NMOS的栅极 在前一级晶体管对的晶体管和晶体管对的PMOS晶体管的栅极处于下一级; 第一至第N PMOS晶体管，适于将第一至第N存储节点之间的相应存储节点驱动到高电平; 以及适用于将第一至第N存储节点之间的相应存储节点驱动到低电平的第一至第N NMOS晶体管。

    SEMICONDUCTOR MEMORY DEVICE, REFRESH CONTROL SYSTEM, AND REFRESH CONTROL METHOD
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, REFRESH CONTROL SYSTEM, AND REFRESH CONTROL METHOD 审中-公开
    半导体存储器件，刷新控制系统和刷新控制方法

    公开(公告)号：US20150155025A1

    公开(公告)日：2015-06-04

    申请号：US14297336

    申请日：2014-06-05

    Applicant: SK hynix Inc.

    Inventor： Jae-Seung LEE ,  Choung-Ki SONG

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G11C11/40611

    Abstract: A semiconductor memory device includes a normal command generation unit suitable for generating a normal refresh command in response to a refresh command; a smart command generation unit suitable for performing a counting operation on the refresh command to generate a plurality of smart refresh commands which are activated at a predetermined period; and a refresh operation unit suitable for performing a refresh operation in response to the normal refresh command and the plurality of smart refresh commands, wherein the smart command generation unit resets the counting operation when entering into the refresh operation.

    Abstract translation: 半导体存储器件包括：适于根据刷新命令生成正常刷新命令的正常命令生成单元; 智能命令生成单元，其适于对所述刷新命令进行计数操作，以生成在预定周期被激活的多个智能刷新命令; 以及适用于响应于正常刷新命令和多个智能刷新命令执行刷新操作的刷新操作单元，其中智能命令生成单元在进入刷新操作时复位计数操作。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200160903A1

    公开(公告)日：2020-05-21

    申请号：US16751392

    申请日：2020-01-24

    Applicant: SK hynix Inc.

    Inventor： Jae-Seung LEE ,  No-Geun JOO

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

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